@SIM_ENABLE_ARCH_frv_TRUE@am__append_49 = frv/eng.h
@SIM_ENABLE_ARCH_frv_TRUE@am__append_50 = $(frv_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_frv_TRUE@am__append_51 = $(frv_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_ft32_TRUE@am__append_52 = ft32/run
-@SIM_ENABLE_ARCH_h8300_TRUE@am__append_53 = h8300/run
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_54 = iq2000/run
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_55 = iq2000/eng.h
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_56 = $(iq2000_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_57 = $(iq2000_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_58 = lm32/run
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_59 = lm32_SIM_EXTRA_HW_DEVICES="$(lm32_SIM_EXTRA_HW_DEVICES)"
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_60 = lm32/eng.h
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_61 = $(lm32_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_62 = $(lm32_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_63 = m32c/run
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_64 = $(m32c_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_65 = m32c/opc2c
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_66 = \
+@SIM_ENABLE_ARCH_ft32_TRUE@am__append_52 = ft32/libsim.a
+@SIM_ENABLE_ARCH_ft32_TRUE@am__append_53 = ft32/run
+@SIM_ENABLE_ARCH_h8300_TRUE@am__append_54 = h8300/libsim.a
+@SIM_ENABLE_ARCH_h8300_TRUE@am__append_55 = h8300/run
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_56 = iq2000/libsim.a
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_57 = iq2000/run
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_58 = iq2000/eng.h
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_59 = $(iq2000_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_60 = $(iq2000_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_61 = lm32/libsim.a
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_62 = lm32/run
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_63 = lm32_SIM_EXTRA_HW_DEVICES="$(lm32_SIM_EXTRA_HW_DEVICES)"
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_64 = lm32/eng.h
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_65 = $(lm32_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_66 = $(lm32_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_67 = m32c/libsim.a
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_68 = m32c/run
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_69 = $(m32c_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_70 = m32c/opc2c
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_71 = \
@SIM_ENABLE_ARCH_m32c_TRUE@ $(m32c_BUILD_OUTPUTS) \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/m32c.c.log \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/r8c.c.log
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_67 = m32r/run
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_68 = m32r_SIM_EXTRA_HW_DEVICES="$(m32r_SIM_EXTRA_HW_DEVICES)"
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_69 = \
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_72 = m32r/libsim.a
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_73 = m32r/run
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_74 = m32r_SIM_EXTRA_HW_DEVICES="$(m32r_SIM_EXTRA_HW_DEVICES)"
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_75 = \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/eng.h \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/engx.h \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/eng2.h
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_70 = $(m32r_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_71 = $(m32r_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_72 = m68hc11/run
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_73 = m68hc11_SIM_EXTRA_HW_DEVICES="$(m68hc11_SIM_EXTRA_HW_DEVICES)"
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_74 = $(m68hc11_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_75 = m68hc11/gencode
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_76 = $(m68hc11_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_mcore_TRUE@am__append_77 = mcore/run
-@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_78 = microblaze/run
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_79 = mips/run
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_80 = mips_SIM_EXTRA_HW_DEVICES="$(mips_SIM_EXTRA_HW_DEVICES)"
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_81 = mips/itable.h \
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_76 = $(m32r_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_77 = $(m32r_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_78 = m68hc11/libsim.a
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_79 = m68hc11/run
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_80 = m68hc11_SIM_EXTRA_HW_DEVICES="$(m68hc11_SIM_EXTRA_HW_DEVICES)"
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_81 = $(m68hc11_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_82 = m68hc11/gencode
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_83 = $(m68hc11_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_mcore_TRUE@am__append_84 = mcore/libsim.a
+@SIM_ENABLE_ARCH_mcore_TRUE@am__append_85 = mcore/run
+@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_86 = microblaze/libsim.a
+@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_87 = microblaze/run
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_88 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/support.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/itable.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/semantics.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/idecode.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/icache.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/engine.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/irun.o
+
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_89 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_support.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_semantics.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_idecode.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_icache.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m32_support.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m32_semantics.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m32_idecode.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m32_icache.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/itable.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16run.o
+
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_90 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ $(SIM_MIPS_MULTI_OBJ) \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/itable.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/multi-run.o
+
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_91 = mips/libsim.a
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_92 = mips/run
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_93 = mips_SIM_EXTRA_HW_DEVICES="$(mips_SIM_EXTRA_HW_DEVICES)"
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_94 = mips/itable.h \
@SIM_ENABLE_ARCH_mips_TRUE@ $(SIM_MIPS_MULTI_SRC)
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_82 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_95 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ $(mips_BUILT_SRC_FROM_GEN_MODE_SINGLE) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/stamp-gen-mode-single
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_83 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_96 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ $(mips_BUILT_SRC_FROM_GEN_MODE_M16_M16) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ $(mips_BUILT_SRC_FROM_GEN_MODE_M16_M32) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/stamp-gen-mode-m16-m16 \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/stamp-gen-mode-m16-m32
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_84 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_97 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ $(SIM_MIPS_MULTI_SRC) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/stamp-gen-mode-multi-igen \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/stamp-gen-mode-multi-run
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_85 = $(mips_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_86 = $(mips_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_87 = mips/multi-include.h mips/multi-run.c
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_88 = mn10300/run
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_89 = mn10300_SIM_EXTRA_HW_DEVICES="$(mn10300_SIM_EXTRA_HW_DEVICES)"
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_90 = \
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_98 = $(mips_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_99 = $(mips_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_100 = mips/multi-include.h mips/multi-run.c
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_101 = mn10300/libsim.a
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_102 = mn10300/run
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_103 = mn10300_SIM_EXTRA_HW_DEVICES="$(mn10300_SIM_EXTRA_HW_DEVICES)"
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_104 = \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/idecode.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/engine.h
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_91 = $(mn10300_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_92 = $(mn10300_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_moxie_TRUE@am__append_93 = moxie/run
-@SIM_ENABLE_ARCH_msp430_TRUE@am__append_94 = msp430/run
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_95 = or1k/run
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_96 = or1k/eng.h
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_97 = $(or1k_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_98 = $(or1k_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_ppc_TRUE@am__append_99 = ppc/run ppc/psim
-@SIM_ENABLE_ARCH_pru_TRUE@am__append_100 = pru/run
-@SIM_ENABLE_ARCH_riscv_TRUE@am__append_101 = riscv/run
-@SIM_ENABLE_ARCH_rl78_TRUE@am__append_102 = rl78/run
-@SIM_ENABLE_ARCH_rx_TRUE@am__append_103 = rx/run
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_104 = sh/run
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_105 = \
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_105 = $(mn10300_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_106 = $(mn10300_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_moxie_TRUE@am__append_107 = moxie/libsim.a
+@SIM_ENABLE_ARCH_moxie_TRUE@am__append_108 = moxie/run
+@SIM_ENABLE_ARCH_msp430_TRUE@am__append_109 = msp430/libsim.a
+@SIM_ENABLE_ARCH_msp430_TRUE@am__append_110 = msp430/run
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_111 = or1k/libsim.a
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_112 = or1k/run
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_113 = or1k/eng.h
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_114 = $(or1k_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_115 = $(or1k_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_ppc_TRUE@am__append_116 = ppc/run ppc/psim
+@SIM_ENABLE_ARCH_pru_TRUE@am__append_117 = pru/libsim.a
+@SIM_ENABLE_ARCH_pru_TRUE@am__append_118 = pru/run
+@SIM_ENABLE_ARCH_riscv_TRUE@am__append_119 = riscv/libsim.a
+@SIM_ENABLE_ARCH_riscv_TRUE@am__append_120 = riscv/run
+@SIM_ENABLE_ARCH_rl78_TRUE@am__append_121 = rl78/libsim.a
+@SIM_ENABLE_ARCH_rl78_TRUE@am__append_122 = rl78/run
+@SIM_ENABLE_ARCH_rx_TRUE@am__append_123 = rx/libsim.a
+@SIM_ENABLE_ARCH_rx_TRUE@am__append_124 = rx/run
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_125 = sh/libsim.a
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_126 = sh/run
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_127 = \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/code.c \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/ppi.c
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_106 = $(sh_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_107 = sh/gencode
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_108 = $(sh_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_109 = v850/run
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_110 = \
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_128 = $(sh_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_129 = sh/gencode
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_130 = $(sh_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_131 = v850/libsim.a
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_132 = v850/run
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_133 = \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/icache.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/idecode.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/semantics.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/itable.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/engine.h
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_111 = $(v850_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_112 = $(v850_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_134 = $(v850_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_135 = $(v850_BUILD_OUTPUTS)
subdir = .
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/reset.o frv/sim-if.o frv/traps.o
am_frv_libsim_a_OBJECTS =
frv_libsim_a_OBJECTS = $(am_frv_libsim_a_OBJECTS)
+ft32_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_ft32_TRUE@ft32_libsim_a_DEPENDENCIES = \
+@SIM_ENABLE_ARCH_ft32_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_ft32_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_ft32_TRUE@ %,ft32/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_ft32_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_ft32_TRUE@ %,ft32/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_ft32_TRUE@ ft32/interp.o ft32/modules.o \
+@SIM_ENABLE_ARCH_ft32_TRUE@ ft32/sim-resume.o
+am_ft32_libsim_a_OBJECTS =
+ft32_libsim_a_OBJECTS = $(am_ft32_libsim_a_OBJECTS)
+h8300_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_h8300_TRUE@h8300_libsim_a_DEPENDENCIES = \
+@SIM_ENABLE_ARCH_h8300_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_h8300_TRUE@ h8300/compile.o $(patsubst \
+@SIM_ENABLE_ARCH_h8300_TRUE@ %,h8300/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_h8300_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_h8300_TRUE@ %,h8300/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_h8300_TRUE@ h8300/modules.o h8300/sim-resume.o
+am_h8300_libsim_a_OBJECTS =
+h8300_libsim_a_OBJECTS = $(am_h8300_libsim_a_OBJECTS)
igen_libigen_a_AR = $(AR) $(ARFLAGS)
igen_libigen_a_LIBADD =
@SIM_ENABLE_IGEN_TRUE@am_igen_libigen_a_OBJECTS = \
@SIM_ENABLE_IGEN_TRUE@ igen/gen-engine.$(OBJEXT) \
@SIM_ENABLE_IGEN_TRUE@ igen/gen.$(OBJEXT)
igen_libigen_a_OBJECTS = $(am_igen_libigen_a_OBJECTS)
+iq2000_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_libsim_a_DEPENDENCIES = \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ %,iq2000/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ %,iq2000/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/modules.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cgen-run.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cgen-scache.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cgen-trace.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cgen-utils.o iq2000/arch.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cpu.o iq2000/decode.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/iq2000.o iq2000/sem.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/mloop.o iq2000/model.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/sim-if.o
+am_iq2000_libsim_a_OBJECTS =
+iq2000_libsim_a_OBJECTS = $(am_iq2000_libsim_a_OBJECTS)
+lm32_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_lm32_TRUE@lm32_libsim_a_DEPENDENCIES = \
+@SIM_ENABLE_ARCH_lm32_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_lm32_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_lm32_TRUE@ %,lm32/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_lm32_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_lm32_TRUE@ %,lm32/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_lm32_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_lm32_TRUE@ %,lm32/dv-%.o,$(lm32_SIM_EXTRA_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/modules.o lm32/cgen-run.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cgen-scache.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cgen-trace.o lm32/cgen-utils.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/arch.o lm32/cpu.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/decode.o lm32/sem.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/mloop.o lm32/model.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/lm32.o lm32/sim-if.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/traps.o lm32/user.o
+am_lm32_libsim_a_OBJECTS =
+lm32_libsim_a_OBJECTS = $(am_lm32_libsim_a_OBJECTS)
+m32c_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_m32c_TRUE@m32c_libsim_a_DEPENDENCIES = \
+@SIM_ENABLE_ARCH_m32c_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/gdb-if.o m32c/int.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/load.o m32c/m32c.o m32c/mem.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/misc.o m32c/modules.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/r8c.o m32c/reg.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/srcdest.o m32c/syscalls.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/trace.o
+am_m32c_libsim_a_OBJECTS =
+m32c_libsim_a_OBJECTS = $(am_m32c_libsim_a_OBJECTS)
+m32r_libsim_a_AR = $(AR) $(ARFLAGS)
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+@SIM_ENABLE_ARCH_m32r_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_m32r_TRUE@ $(patsubst \
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+@SIM_ENABLE_ARCH_m32r_TRUE@ $(patsubst \
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+@SIM_ENABLE_ARCH_m32r_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_m32r_TRUE@ %,m32r/dv-%.o,$(m32r_SIM_EXTRA_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/modules.o m32r/cgen-run.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-scache.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-trace.o m32r/cgen-utils.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/arch.o m32r/m32r.o m32r/cpu.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/decode.o m32r/sem.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/model.o m32r/mloop.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/m32rx.o m32r/cpux.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/decodex.o m32r/modelx.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloopx.o m32r/m32r2.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cpu2.o m32r/decode2.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/model2.o m32r/mloop2.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/sim-if.o m32r/traps.o
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+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/interp.o \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc11int.o \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc12int.o \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/emulos.o \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/interrupts.o \
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+@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ %,m68hc11/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(patsubst \
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+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/modules.o \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/sim-resume.o
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+mcore_libsim_a_AR = $(AR) $(ARFLAGS)
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+@SIM_ENABLE_ARCH_mcore_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/interp.o $(patsubst \
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+@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/modules.o mcore/sim-resume.o
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+@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/interp.o \
+@SIM_ENABLE_ARCH_microblaze_TRUE@ $(patsubst \
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+@SIM_ENABLE_ARCH_microblaze_TRUE@ $(patsubst \
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+@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/modules.o \
+@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/sim-resume.o
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+mips_libsim_a_AR = $(AR) $(ARFLAGS)
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+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/itable.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/multi-run.o
+@SIM_ENABLE_ARCH_mips_TRUE@am__DEPENDENCIES_3 = $(am__append_88) \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_89) \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(am__DEPENDENCIES_2)
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+@SIM_ENABLE_ARCH_mips_TRUE@ mips/interp.o $(am__DEPENDENCIES_3) \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(patsubst \
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+@SIM_ENABLE_ARCH_mips_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_mips_TRUE@ %,mips/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(patsubst \
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+@SIM_ENABLE_ARCH_mips_TRUE@ mips/cp1.o mips/dsp.o mips/mdmx.o \
+@SIM_ENABLE_ARCH_mips_TRUE@ mips/modules.o mips/sim-main.o \
+@SIM_ENABLE_ARCH_mips_TRUE@ mips/sim-resume.o
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+mn10300_libsim_a_AR = $(AR) $(ARFLAGS)
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+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.o \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.o \
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+@SIM_ENABLE_ARCH_mn10300_TRUE@ $(patsubst \
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+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/op_utils.o \
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+mn10300_libsim_a_OBJECTS = $(am_mn10300_libsim_a_OBJECTS)
+moxie_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_moxie_TRUE@moxie_libsim_a_DEPENDENCIES = \
+@SIM_ENABLE_ARCH_moxie_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_moxie_TRUE@ $(patsubst \
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+@SIM_ENABLE_ARCH_moxie_TRUE@ $(patsubst \
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+@SIM_ENABLE_ARCH_moxie_TRUE@ moxie/interp.o moxie/modules.o \
+@SIM_ENABLE_ARCH_moxie_TRUE@ moxie/sim-resume.o
+am_moxie_libsim_a_OBJECTS =
+moxie_libsim_a_OBJECTS = $(am_moxie_libsim_a_OBJECTS)
+msp430_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_msp430_TRUE@msp430_libsim_a_DEPENDENCIES = \
+@SIM_ENABLE_ARCH_msp430_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_msp430_TRUE@ $(patsubst \
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+@SIM_ENABLE_ARCH_msp430_TRUE@ $(patsubst \
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+@SIM_ENABLE_ARCH_msp430_TRUE@ msp430/msp430-sim.o \
+@SIM_ENABLE_ARCH_msp430_TRUE@ msp430/modules.o \
+@SIM_ENABLE_ARCH_msp430_TRUE@ msp430/sim-resume.o
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+@SIM_ENABLE_ARCH_or1k_TRUE@or1k_libsim_a_DEPENDENCIES = \
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+@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/modules.o or1k/cgen-accfp.o \
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+@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/arch.o or1k/cpu.o \
+@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/decode.o or1k/mloop.o \
+@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/model.o or1k/sem.o or1k/or1k.o \
+@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/sim-if.o or1k/traps.o
+am_or1k_libsim_a_OBJECTS =
+or1k_libsim_a_OBJECTS = $(am_or1k_libsim_a_OBJECTS)
+pru_libsim_a_AR = $(AR) $(ARFLAGS)
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+@SIM_ENABLE_ARCH_pru_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_pru_TRUE@ $(patsubst \
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+@SIM_ENABLE_ARCH_pru_TRUE@ pru/interp.o pru/modules.o \
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+riscv_libsim_a_AR = $(AR) $(ARFLAGS)
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+@SIM_ENABLE_ARCH_riscv_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_riscv_TRUE@ $(patsubst \
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+@SIM_ENABLE_ARCH_riscv_TRUE@ $(patsubst \
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+@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/interp.o riscv/machs.o \
+@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/modules.o riscv/sim-main.o \
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+rl78_libsim_a_AR = $(AR) $(ARFLAGS)
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+@SIM_ENABLE_ARCH_rx_TRUE@ rx/fpu.o rx/load.o rx/mem.o rx/misc.o \
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+@SIM_ENABLE_ARCH_rx_TRUE@ rx/trace.o rx/gdb-if.o rx/err.o \
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+sh_libsim_a_AR = $(AR) $(ARFLAGS)
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+@SIM_ENABLE_ARCH_sh_TRUE@ sh/interp.o $(patsubst \
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+@SIM_ENABLE_ARCH_v850_TRUE@ v850/support.o v850/modules.o \
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@SIM_ENABLE_IGEN_TRUE@ igen/gen$(EXEEXT) igen/ld-cache$(EXEEXT) \
@SIM_ENABLE_IGEN_TRUE@ igen/ld-decode$(EXEEXT) \
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aarch64_run_OBJECTS = $(am_aarch64_run_OBJECTS)
-am__DEPENDENCIES_1 = $(BFD_LIB) $(OPCODES_LIB) $(LIBIBERTY_LIB)
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@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_run_DEPENDENCIES = \
@SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/nrun.o aarch64/libsim.a \
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AM_V_lt = $(am__v_lt_@AM_V@)
am__v_lt_ = $(am__v_lt_@AM_DEFAULT_V@)
am__v_lt_0 = --silent
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@SIM_ENABLE_ARCH_arm_TRUE@arm_run_DEPENDENCIES = arm/nrun.o \
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@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/libsim.a \
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@SIM_ENABLE_ARCH_erc32_TRUE@ $(am__DEPENDENCIES_1) \
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erc32_sis_OBJECTS = erc32/sis.$(OBJEXT)
erc32_sis_LDADD = $(LDADD)
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@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/nrun.o \
@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/libsim.a \
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+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cgen-scache.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cgen-trace.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cgen-utils.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/arch.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cpu.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/decode.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/iq2000.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/sem.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/mloop.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/model.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/sim-if.o
+
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_run_SOURCES =
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_run_LDADD = \
@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/nrun.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/mloop.c \
@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/stamp-mloop
+@SIM_ENABLE_ARCH_lm32_TRUE@lm32_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_lm32_TRUE@lm32_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_lm32_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_lm32_TRUE@ $(patsubst %,lm32/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_lm32_TRUE@ $(patsubst %,lm32/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_lm32_TRUE@ $(patsubst %,lm32/dv-%.o,$(lm32_SIM_EXTRA_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/modules.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cgen-run.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cgen-scache.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cgen-trace.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cgen-utils.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/arch.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cpu.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/decode.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/sem.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/mloop.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/model.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/lm32.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/sim-if.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/traps.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/user.o
+
@SIM_ENABLE_ARCH_lm32_TRUE@lm32_run_SOURCES =
@SIM_ENABLE_ARCH_lm32_TRUE@lm32_run_LDADD = \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/nrun.o \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/mloop.c \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/stamp-mloop
+@SIM_ENABLE_ARCH_m32c_TRUE@AM_CPPFLAGS_m32c = -DTIMER_A
+@SIM_ENABLE_ARCH_m32c_TRUE@m32c_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_m32c_TRUE@m32c_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_m32c_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/gdb-if.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/int.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/load.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/m32c.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/mem.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/misc.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/modules.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/r8c.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/reg.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/srcdest.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/syscalls.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/trace.o
+
@SIM_ENABLE_ARCH_m32c_TRUE@m32c_run_SOURCES =
@SIM_ENABLE_ARCH_m32c_TRUE@m32c_run_LDADD = \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/main.o \
# opc2c leaks memory, and therefore makes AddressSanitizer unhappy. Disable
# leak detection while running it.
@SIM_ENABLE_ARCH_m32c_TRUE@m32c_OPC2C_RUN = ASAN_OPTIONS=detect_leaks=0 m32c/opc2c$(EXEEXT)
+@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_cpu.o = -Wno-error
+@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_cpu2.o = -Wno-error
+@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_cpux.o = -Wno-error
+@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_m32r.o = -Wno-error
+@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_m32r2.o = -Wno-error
+@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_m32rx.o = -Wno-error
+@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_mloop.o = -Wno-error
+@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_mloop2.o = -Wno-error
+@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_mloopx.o = -Wno-error
+@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_sem.o = -Wno-error
+@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_sim_if.o = -Wno-error
+@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_traps.o = -Wno-error
+@SIM_ENABLE_ARCH_m32r_TRUE@m32r_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_m32r_TRUE@m32r_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_m32r_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_m32r_TRUE@ $(patsubst %,m32r/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_m32r_TRUE@ $(patsubst %,m32r/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_m32r_TRUE@ $(patsubst %,m32r/dv-%.o,$(m32r_SIM_EXTRA_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/modules.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-run.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-scache.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-trace.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-utils.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/arch.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/m32r.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cpu.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/decode.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/sem.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/model.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloop.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/m32rx.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cpux.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/decodex.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/modelx.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloopx.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/m32r2.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cpu2.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/decode2.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/model2.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloop2.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/sim-if.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/traps.o
+
@SIM_ENABLE_ARCH_m32r_TRUE@m32r_run_SOURCES =
@SIM_ENABLE_ARCH_m32r_TRUE@m32r_run_LDADD = \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/nrun.o \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloop2.c \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/stamp-mloop-2
+@SIM_ENABLE_ARCH_m68hc11_TRUE@AM_CPPFLAGS_m68hc11 = \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ -DWITH_TARGET_WORD_BITSIZE=32 \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ -DWITH_TARGET_CELL_BITSIZE=32 \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ -DWITH_TARGET_ADDRESS_BITSIZE=32 \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ -DWITH_TARGET_WORD_MSB=31
+
+@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/interp.o \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc11int.o \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc12int.o \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/emulos.o \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/interrupts.o \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc11_sim.o \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(patsubst %,m68hc11/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(patsubst %,m68hc11/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(patsubst %,m68hc11/dv-%.o,$(m68hc11_SIM_EXTRA_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/modules.o \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/sim-resume.o
+
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_run_SOURCES =
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_run_LDADD = \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/nrun.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc12int.c
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_gencode_SOURCES = m68hc11/gencode.c
+@SIM_ENABLE_ARCH_mcore_TRUE@mcore_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_mcore_TRUE@mcore_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_mcore_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/interp.o \
+@SIM_ENABLE_ARCH_mcore_TRUE@ $(patsubst %,mcore/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_mcore_TRUE@ $(patsubst %,mcore/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/modules.o \
+@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/sim-resume.o
+
@SIM_ENABLE_ARCH_mcore_TRUE@mcore_run_SOURCES =
@SIM_ENABLE_ARCH_mcore_TRUE@mcore_run_LDADD = \
@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/nrun.o \
@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/libsim.a \
@SIM_ENABLE_ARCH_mcore_TRUE@ $(SIM_COMMON_LIBS)
+@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_microblaze_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/interp.o \
+@SIM_ENABLE_ARCH_microblaze_TRUE@ $(patsubst %,microblaze/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_microblaze_TRUE@ $(patsubst %,microblaze/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/modules.o \
+@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/sim-resume.o
+
@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_run_SOURCES =
@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_run_LDADD = \
@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/nrun.o \
@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/libsim.a \
@SIM_ENABLE_ARCH_microblaze_TRUE@ $(SIM_COMMON_LIBS)
+@SIM_ENABLE_ARCH_mips_TRUE@AM_CPPFLAGS_mips = \
+@SIM_ENABLE_ARCH_mips_TRUE@ @SIM_MIPS_SUBTARGET@ \
+@SIM_ENABLE_ARCH_mips_TRUE@ -DWITH_TARGET_WORD_BITSIZE=@SIM_MIPS_BITSIZE@ -DWITH_TARGET_WORD_MSB=WITH_TARGET_WORD_BITSIZE-1 \
+@SIM_ENABLE_ARCH_mips_TRUE@ -DWITH_FLOATING_POINT=HARD_FLOATING_POINT -DWITH_TARGET_FLOATING_POINT_BITSIZE=@SIM_MIPS_FPU_BITSIZE@
+
+@SIM_ENABLE_ARCH_mips_TRUE@mips_GEN_OBJ = $(am__append_88) \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_89) $(am__append_90)
+@SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_mips_TRUE@ mips/interp.o \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(mips_GEN_OBJ) \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(patsubst %,mips/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(patsubst %,mips/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(patsubst %,mips/dv-%.o,$(mips_SIM_EXTRA_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_mips_TRUE@ mips/cp1.o \
+@SIM_ENABLE_ARCH_mips_TRUE@ mips/dsp.o \
+@SIM_ENABLE_ARCH_mips_TRUE@ mips/mdmx.o \
+@SIM_ENABLE_ARCH_mips_TRUE@ mips/modules.o \
+@SIM_ENABLE_ARCH_mips_TRUE@ mips/sim-main.o \
+@SIM_ENABLE_ARCH_mips_TRUE@ mips/sim-resume.o
+
+@SIM_ENABLE_ARCH_mips_TRUE@EXTRA_mips_libsim_a_DEPENDENCIES = $(SIM_MIPS_MULTI_OBJ)
@SIM_ENABLE_ARCH_mips_TRUE@mips_run_SOURCES =
@SIM_ENABLE_ARCH_mips_TRUE@mips_run_LDADD = \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/nrun.o \
@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_mips_TRUE@ $(mips_BUILT_SRC_FROM_IGEN_ITABLE) \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/stamp-igen-itable \
-@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_82) $(am__append_83) \
-@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_84)
+@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_95) $(am__append_96) \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_97)
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-all
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN = $(srcdir)/mips/mips.igen
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN_INC = \
@SIM_ENABLE_ARCH_mips_TRUE@mips_M16_DC = $(srcdir)/mips/m16.dc
@SIM_ENABLE_ARCH_mips_TRUE@mips_MICROMIPS32_DC = $(srcdir)/mips/micromips.dc
@SIM_ENABLE_ARCH_mips_TRUE@mips_MICROMIPS16_DC = $(srcdir)/mips/micromips16.dc
+@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.o \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.o \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/idecode.o \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.o \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/engine.o \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/irun.o \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/support.o \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ $(patsubst %,mn10300/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ $(patsubst %,mn10300/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ $(patsubst %,mn10300/dv-%.o,$(mn10300_SIM_EXTRA_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/interp.o \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/modules.o \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/op_utils.o \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/sim-resume.o
+
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_run_SOURCES =
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_run_LDADD = \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/nrun.o \
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_IGEN_INSN = $(srcdir)/mn10300/mn10300.igen
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_IGEN_INSN_INC = mn10300/am33.igen mn10300/am33-2.igen
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_IGEN_DC = $(srcdir)/mn10300/mn10300.dc
+@SIM_ENABLE_ARCH_moxie_TRUE@moxie_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_moxie_TRUE@moxie_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_moxie_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_moxie_TRUE@ $(patsubst %,moxie/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_moxie_TRUE@ $(patsubst %,moxie/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_moxie_TRUE@ moxie/interp.o \
+@SIM_ENABLE_ARCH_moxie_TRUE@ moxie/modules.o \
+@SIM_ENABLE_ARCH_moxie_TRUE@ moxie/sim-resume.o
+
@SIM_ENABLE_ARCH_moxie_TRUE@moxie_run_SOURCES =
@SIM_ENABLE_ARCH_moxie_TRUE@moxie_run_LDADD = \
@SIM_ENABLE_ARCH_moxie_TRUE@ moxie/nrun.o \
@SIM_ENABLE_ARCH_moxie_TRUE@dtbdir = $(datadir)/gdb/dtb
@SIM_ENABLE_ARCH_moxie_TRUE@dtb_DATA = moxie/moxie-gdb.dtb
+@SIM_ENABLE_ARCH_msp430_TRUE@msp430_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_msp430_TRUE@msp430_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_msp430_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_msp430_TRUE@ $(patsubst %,msp430/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_msp430_TRUE@ $(patsubst %,msp430/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_msp430_TRUE@ msp430/msp430-sim.o \
+@SIM_ENABLE_ARCH_msp430_TRUE@ msp430/modules.o \
+@SIM_ENABLE_ARCH_msp430_TRUE@ msp430/sim-resume.o
+
@SIM_ENABLE_ARCH_msp430_TRUE@msp430_run_SOURCES =
@SIM_ENABLE_ARCH_msp430_TRUE@msp430_run_LDADD = \
@SIM_ENABLE_ARCH_msp430_TRUE@ msp430/nrun.o \
@SIM_ENABLE_ARCH_msp430_TRUE@ msp430/libsim.a \
@SIM_ENABLE_ARCH_msp430_TRUE@ $(SIM_COMMON_LIBS)
+@SIM_ENABLE_ARCH_or1k_TRUE@or1k_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_or1k_TRUE@or1k_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_or1k_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_or1k_TRUE@ $(patsubst %,or1k/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_or1k_TRUE@ $(patsubst %,or1k/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/modules.o \
+@SIM_ENABLE_ARCH_or1k_TRUE@ \
+@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cgen-accfp.o \
+@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cgen-fpu.o \
+@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cgen-run.o \
+@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cgen-scache.o \
+@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cgen-trace.o \
+@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cgen-utils.o \
+@SIM_ENABLE_ARCH_or1k_TRUE@ \
+@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/arch.o \
+@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cpu.o \
+@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/decode.o \
+@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/mloop.o \
+@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/model.o \
+@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/sem.o \
+@SIM_ENABLE_ARCH_or1k_TRUE@ \
+@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/or1k.o \
+@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/sim-if.o \
+@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/traps.o
+
@SIM_ENABLE_ARCH_or1k_TRUE@or1k_run_SOURCES =
@SIM_ENABLE_ARCH_or1k_TRUE@or1k_run_LDADD = \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/nrun.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ppcdocdir = $(docdir)/ppc
@SIM_ENABLE_ARCH_ppc_TRUE@ppcdoc_DATA = ppc/BUGS ppc/INSTALL ppc/README ppc/RUN
+@SIM_ENABLE_ARCH_pru_TRUE@pru_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_pru_TRUE@pru_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_pru_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_pru_TRUE@ $(patsubst %,pru/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_pru_TRUE@ $(patsubst %,pru/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_pru_TRUE@ pru/interp.o \
+@SIM_ENABLE_ARCH_pru_TRUE@ pru/modules.o \
+@SIM_ENABLE_ARCH_pru_TRUE@ pru/sim-resume.o
+
@SIM_ENABLE_ARCH_pru_TRUE@pru_run_SOURCES =
@SIM_ENABLE_ARCH_pru_TRUE@pru_run_LDADD = \
@SIM_ENABLE_ARCH_pru_TRUE@ pru/nrun.o \
@SIM_ENABLE_ARCH_pru_TRUE@ pru/libsim.a \
@SIM_ENABLE_ARCH_pru_TRUE@ $(SIM_COMMON_LIBS)
+@SIM_ENABLE_ARCH_riscv_TRUE@riscv_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_riscv_TRUE@riscv_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_riscv_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_riscv_TRUE@ $(patsubst %,riscv/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_riscv_TRUE@ $(patsubst %,riscv/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/interp.o \
+@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/machs.o \
+@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/modules.o \
+@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/sim-main.o \
+@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/sim-resume.o
+
@SIM_ENABLE_ARCH_riscv_TRUE@riscv_run_SOURCES =
@SIM_ENABLE_ARCH_riscv_TRUE@riscv_run_LDADD = \
@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/nrun.o \
@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/libsim.a \
@SIM_ENABLE_ARCH_riscv_TRUE@ $(SIM_COMMON_LIBS)
+@SIM_ENABLE_ARCH_rl78_TRUE@rl78_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_rl78_TRUE@rl78_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_rl78_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/load.o \
+@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/mem.o \
+@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/cpu.o \
+@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/rl78.o \
+@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/gdb-if.o \
+@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/modules.o \
+@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/trace.o
+
@SIM_ENABLE_ARCH_rl78_TRUE@rl78_run_SOURCES =
@SIM_ENABLE_ARCH_rl78_TRUE@rl78_run_LDADD = \
@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/main.o \
@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/libsim.a \
@SIM_ENABLE_ARCH_rl78_TRUE@ $(SIM_COMMON_LIBS)
+@SIM_ENABLE_ARCH_rx_TRUE@rx_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_rx_TRUE@rx_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_rx_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_rx_TRUE@ rx/fpu.o \
+@SIM_ENABLE_ARCH_rx_TRUE@ rx/load.o \
+@SIM_ENABLE_ARCH_rx_TRUE@ rx/mem.o \
+@SIM_ENABLE_ARCH_rx_TRUE@ rx/misc.o \
+@SIM_ENABLE_ARCH_rx_TRUE@ rx/reg.o \
+@SIM_ENABLE_ARCH_rx_TRUE@ rx/rx.o \
+@SIM_ENABLE_ARCH_rx_TRUE@ rx/syscalls.o \
+@SIM_ENABLE_ARCH_rx_TRUE@ rx/trace.o \
+@SIM_ENABLE_ARCH_rx_TRUE@ rx/gdb-if.o \
+@SIM_ENABLE_ARCH_rx_TRUE@ rx/err.o \
+@SIM_ENABLE_ARCH_rx_TRUE@ rx/modules.o
+
@SIM_ENABLE_ARCH_rx_TRUE@rx_run_SOURCES =
@SIM_ENABLE_ARCH_rx_TRUE@rx_run_LDADD = \
@SIM_ENABLE_ARCH_rx_TRUE@ rx/main.o \
@SIM_ENABLE_ARCH_rx_TRUE@rxdocdir = $(docdir)/rx
@SIM_ENABLE_ARCH_rx_TRUE@rxdoc_DATA = rx/README.txt
+@SIM_ENABLE_ARCH_sh_TRUE@sh_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_sh_TRUE@sh_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_sh_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_sh_TRUE@ sh/interp.o \
+@SIM_ENABLE_ARCH_sh_TRUE@ $(patsubst %,sh/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_sh_TRUE@ $(patsubst %,sh/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_sh_TRUE@ sh/modules.o \
+@SIM_ENABLE_ARCH_sh_TRUE@ sh/table.o
+
@SIM_ENABLE_ARCH_sh_TRUE@sh_run_SOURCES =
@SIM_ENABLE_ARCH_sh_TRUE@sh_run_LDADD = \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/nrun.o \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/table.c
@SIM_ENABLE_ARCH_sh_TRUE@sh_gencode_SOURCES = sh/gencode.c
+@SIM_ENABLE_ARCH_v850_TRUE@v850_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_v850_TRUE@v850_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_v850_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_v850_TRUE@ $(patsubst %,v850/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_v850_TRUE@ $(patsubst %,v850/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_v850_TRUE@ v850/simops.o \
+@SIM_ENABLE_ARCH_v850_TRUE@ v850/interp.o \
+@SIM_ENABLE_ARCH_v850_TRUE@ v850/itable.o \
+@SIM_ENABLE_ARCH_v850_TRUE@ v850/semantics.o \
+@SIM_ENABLE_ARCH_v850_TRUE@ v850/idecode.o \
+@SIM_ENABLE_ARCH_v850_TRUE@ v850/icache.o \
+@SIM_ENABLE_ARCH_v850_TRUE@ v850/engine.o \
+@SIM_ENABLE_ARCH_v850_TRUE@ v850/irun.o \
+@SIM_ENABLE_ARCH_v850_TRUE@ v850/support.o \
+@SIM_ENABLE_ARCH_v850_TRUE@ v850/modules.o \
+@SIM_ENABLE_ARCH_v850_TRUE@ v850/sim-resume.o
+
@SIM_ENABLE_ARCH_v850_TRUE@v850_run_SOURCES =
@SIM_ENABLE_ARCH_v850_TRUE@v850_run_LDADD = \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/nrun.o \
$(AM_V_at)-rm -f frv/libsim.a
$(AM_V_AR)$(frv_libsim_a_AR) frv/libsim.a $(frv_libsim_a_OBJECTS) $(frv_libsim_a_LIBADD)
$(AM_V_at)$(RANLIB) frv/libsim.a
+ft32/$(am__dirstamp):
+ @$(MKDIR_P) ft32
+ @: > ft32/$(am__dirstamp)
+
+ft32/libsim.a: $(ft32_libsim_a_OBJECTS) $(ft32_libsim_a_DEPENDENCIES) $(EXTRA_ft32_libsim_a_DEPENDENCIES) ft32/$(am__dirstamp)
+ $(AM_V_at)-rm -f ft32/libsim.a
+ $(AM_V_AR)$(ft32_libsim_a_AR) ft32/libsim.a $(ft32_libsim_a_OBJECTS) $(ft32_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) ft32/libsim.a
+h8300/$(am__dirstamp):
+ @$(MKDIR_P) h8300
+ @: > h8300/$(am__dirstamp)
+
+h8300/libsim.a: $(h8300_libsim_a_OBJECTS) $(h8300_libsim_a_DEPENDENCIES) $(EXTRA_h8300_libsim_a_DEPENDENCIES) h8300/$(am__dirstamp)
+ $(AM_V_at)-rm -f h8300/libsim.a
+ $(AM_V_AR)$(h8300_libsim_a_AR) h8300/libsim.a $(h8300_libsim_a_OBJECTS) $(h8300_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) h8300/libsim.a
igen/$(am__dirstamp):
@$(MKDIR_P) igen
@: > igen/$(am__dirstamp)
@SIM_ENABLE_IGEN_FALSE@ $(AM_V_at)-rm -f igen/libigen.a
@SIM_ENABLE_IGEN_FALSE@ $(AM_V_AR)$(igen_libigen_a_AR) igen/libigen.a $(igen_libigen_a_OBJECTS) $(igen_libigen_a_LIBADD)
@SIM_ENABLE_IGEN_FALSE@ $(AM_V_at)$(RANLIB) igen/libigen.a
+iq2000/$(am__dirstamp):
+ @$(MKDIR_P) iq2000
+ @: > iq2000/$(am__dirstamp)
+
+iq2000/libsim.a: $(iq2000_libsim_a_OBJECTS) $(iq2000_libsim_a_DEPENDENCIES) $(EXTRA_iq2000_libsim_a_DEPENDENCIES) iq2000/$(am__dirstamp)
+ $(AM_V_at)-rm -f iq2000/libsim.a
+ $(AM_V_AR)$(iq2000_libsim_a_AR) iq2000/libsim.a $(iq2000_libsim_a_OBJECTS) $(iq2000_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) iq2000/libsim.a
+lm32/$(am__dirstamp):
+ @$(MKDIR_P) lm32
+ @: > lm32/$(am__dirstamp)
+
+lm32/libsim.a: $(lm32_libsim_a_OBJECTS) $(lm32_libsim_a_DEPENDENCIES) $(EXTRA_lm32_libsim_a_DEPENDENCIES) lm32/$(am__dirstamp)
+ $(AM_V_at)-rm -f lm32/libsim.a
+ $(AM_V_AR)$(lm32_libsim_a_AR) lm32/libsim.a $(lm32_libsim_a_OBJECTS) $(lm32_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) lm32/libsim.a
+m32c/$(am__dirstamp):
+ @$(MKDIR_P) m32c
+ @: > m32c/$(am__dirstamp)
+
+m32c/libsim.a: $(m32c_libsim_a_OBJECTS) $(m32c_libsim_a_DEPENDENCIES) $(EXTRA_m32c_libsim_a_DEPENDENCIES) m32c/$(am__dirstamp)
+ $(AM_V_at)-rm -f m32c/libsim.a
+ $(AM_V_AR)$(m32c_libsim_a_AR) m32c/libsim.a $(m32c_libsim_a_OBJECTS) $(m32c_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) m32c/libsim.a
+m32r/$(am__dirstamp):
+ @$(MKDIR_P) m32r
+ @: > m32r/$(am__dirstamp)
+
+m32r/libsim.a: $(m32r_libsim_a_OBJECTS) $(m32r_libsim_a_DEPENDENCIES) $(EXTRA_m32r_libsim_a_DEPENDENCIES) m32r/$(am__dirstamp)
+ $(AM_V_at)-rm -f m32r/libsim.a
+ $(AM_V_AR)$(m32r_libsim_a_AR) m32r/libsim.a $(m32r_libsim_a_OBJECTS) $(m32r_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) m32r/libsim.a
+m68hc11/$(am__dirstamp):
+ @$(MKDIR_P) m68hc11
+ @: > m68hc11/$(am__dirstamp)
+
+m68hc11/libsim.a: $(m68hc11_libsim_a_OBJECTS) $(m68hc11_libsim_a_DEPENDENCIES) $(EXTRA_m68hc11_libsim_a_DEPENDENCIES) m68hc11/$(am__dirstamp)
+ $(AM_V_at)-rm -f m68hc11/libsim.a
+ $(AM_V_AR)$(m68hc11_libsim_a_AR) m68hc11/libsim.a $(m68hc11_libsim_a_OBJECTS) $(m68hc11_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) m68hc11/libsim.a
+mcore/$(am__dirstamp):
+ @$(MKDIR_P) mcore
+ @: > mcore/$(am__dirstamp)
+
+mcore/libsim.a: $(mcore_libsim_a_OBJECTS) $(mcore_libsim_a_DEPENDENCIES) $(EXTRA_mcore_libsim_a_DEPENDENCIES) mcore/$(am__dirstamp)
+ $(AM_V_at)-rm -f mcore/libsim.a
+ $(AM_V_AR)$(mcore_libsim_a_AR) mcore/libsim.a $(mcore_libsim_a_OBJECTS) $(mcore_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) mcore/libsim.a
+microblaze/$(am__dirstamp):
+ @$(MKDIR_P) microblaze
+ @: > microblaze/$(am__dirstamp)
+
+microblaze/libsim.a: $(microblaze_libsim_a_OBJECTS) $(microblaze_libsim_a_DEPENDENCIES) $(EXTRA_microblaze_libsim_a_DEPENDENCIES) microblaze/$(am__dirstamp)
+ $(AM_V_at)-rm -f microblaze/libsim.a
+ $(AM_V_AR)$(microblaze_libsim_a_AR) microblaze/libsim.a $(microblaze_libsim_a_OBJECTS) $(microblaze_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) microblaze/libsim.a
+mips/$(am__dirstamp):
+ @$(MKDIR_P) mips
+ @: > mips/$(am__dirstamp)
+
+mips/libsim.a: $(mips_libsim_a_OBJECTS) $(mips_libsim_a_DEPENDENCIES) $(EXTRA_mips_libsim_a_DEPENDENCIES) mips/$(am__dirstamp)
+ $(AM_V_at)-rm -f mips/libsim.a
+ $(AM_V_AR)$(mips_libsim_a_AR) mips/libsim.a $(mips_libsim_a_OBJECTS) $(mips_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) mips/libsim.a
+mn10300/$(am__dirstamp):
+ @$(MKDIR_P) mn10300
+ @: > mn10300/$(am__dirstamp)
+
+mn10300/libsim.a: $(mn10300_libsim_a_OBJECTS) $(mn10300_libsim_a_DEPENDENCIES) $(EXTRA_mn10300_libsim_a_DEPENDENCIES) mn10300/$(am__dirstamp)
+ $(AM_V_at)-rm -f mn10300/libsim.a
+ $(AM_V_AR)$(mn10300_libsim_a_AR) mn10300/libsim.a $(mn10300_libsim_a_OBJECTS) $(mn10300_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) mn10300/libsim.a
+moxie/$(am__dirstamp):
+ @$(MKDIR_P) moxie
+ @: > moxie/$(am__dirstamp)
+
+moxie/libsim.a: $(moxie_libsim_a_OBJECTS) $(moxie_libsim_a_DEPENDENCIES) $(EXTRA_moxie_libsim_a_DEPENDENCIES) moxie/$(am__dirstamp)
+ $(AM_V_at)-rm -f moxie/libsim.a
+ $(AM_V_AR)$(moxie_libsim_a_AR) moxie/libsim.a $(moxie_libsim_a_OBJECTS) $(moxie_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) moxie/libsim.a
+msp430/$(am__dirstamp):
+ @$(MKDIR_P) msp430
+ @: > msp430/$(am__dirstamp)
+
+msp430/libsim.a: $(msp430_libsim_a_OBJECTS) $(msp430_libsim_a_DEPENDENCIES) $(EXTRA_msp430_libsim_a_DEPENDENCIES) msp430/$(am__dirstamp)
+ $(AM_V_at)-rm -f msp430/libsim.a
+ $(AM_V_AR)$(msp430_libsim_a_AR) msp430/libsim.a $(msp430_libsim_a_OBJECTS) $(msp430_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) msp430/libsim.a
+or1k/$(am__dirstamp):
+ @$(MKDIR_P) or1k
+ @: > or1k/$(am__dirstamp)
+
+or1k/libsim.a: $(or1k_libsim_a_OBJECTS) $(or1k_libsim_a_DEPENDENCIES) $(EXTRA_or1k_libsim_a_DEPENDENCIES) or1k/$(am__dirstamp)
+ $(AM_V_at)-rm -f or1k/libsim.a
+ $(AM_V_AR)$(or1k_libsim_a_AR) or1k/libsim.a $(or1k_libsim_a_OBJECTS) $(or1k_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) or1k/libsim.a
+pru/$(am__dirstamp):
+ @$(MKDIR_P) pru
+ @: > pru/$(am__dirstamp)
+
+pru/libsim.a: $(pru_libsim_a_OBJECTS) $(pru_libsim_a_DEPENDENCIES) $(EXTRA_pru_libsim_a_DEPENDENCIES) pru/$(am__dirstamp)
+ $(AM_V_at)-rm -f pru/libsim.a
+ $(AM_V_AR)$(pru_libsim_a_AR) pru/libsim.a $(pru_libsim_a_OBJECTS) $(pru_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) pru/libsim.a
+riscv/$(am__dirstamp):
+ @$(MKDIR_P) riscv
+ @: > riscv/$(am__dirstamp)
+
+riscv/libsim.a: $(riscv_libsim_a_OBJECTS) $(riscv_libsim_a_DEPENDENCIES) $(EXTRA_riscv_libsim_a_DEPENDENCIES) riscv/$(am__dirstamp)
+ $(AM_V_at)-rm -f riscv/libsim.a
+ $(AM_V_AR)$(riscv_libsim_a_AR) riscv/libsim.a $(riscv_libsim_a_OBJECTS) $(riscv_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) riscv/libsim.a
+rl78/$(am__dirstamp):
+ @$(MKDIR_P) rl78
+ @: > rl78/$(am__dirstamp)
+
+rl78/libsim.a: $(rl78_libsim_a_OBJECTS) $(rl78_libsim_a_DEPENDENCIES) $(EXTRA_rl78_libsim_a_DEPENDENCIES) rl78/$(am__dirstamp)
+ $(AM_V_at)-rm -f rl78/libsim.a
+ $(AM_V_AR)$(rl78_libsim_a_AR) rl78/libsim.a $(rl78_libsim_a_OBJECTS) $(rl78_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) rl78/libsim.a
+rx/$(am__dirstamp):
+ @$(MKDIR_P) rx
+ @: > rx/$(am__dirstamp)
+
+rx/libsim.a: $(rx_libsim_a_OBJECTS) $(rx_libsim_a_DEPENDENCIES) $(EXTRA_rx_libsim_a_DEPENDENCIES) rx/$(am__dirstamp)
+ $(AM_V_at)-rm -f rx/libsim.a
+ $(AM_V_AR)$(rx_libsim_a_AR) rx/libsim.a $(rx_libsim_a_OBJECTS) $(rx_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) rx/libsim.a
+sh/$(am__dirstamp):
+ @$(MKDIR_P) sh
+ @: > sh/$(am__dirstamp)
+
+sh/libsim.a: $(sh_libsim_a_OBJECTS) $(sh_libsim_a_DEPENDENCIES) $(EXTRA_sh_libsim_a_DEPENDENCIES) sh/$(am__dirstamp)
+ $(AM_V_at)-rm -f sh/libsim.a
+ $(AM_V_AR)$(sh_libsim_a_AR) sh/libsim.a $(sh_libsim_a_OBJECTS) $(sh_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) sh/libsim.a
+v850/$(am__dirstamp):
+ @$(MKDIR_P) v850
+ @: > v850/$(am__dirstamp)
+
+v850/libsim.a: $(v850_libsim_a_OBJECTS) $(v850_libsim_a_DEPENDENCIES) $(EXTRA_v850_libsim_a_DEPENDENCIES) v850/$(am__dirstamp)
+ $(AM_V_at)-rm -f v850/libsim.a
+ $(AM_V_AR)$(v850_libsim_a_AR) v850/libsim.a $(v850_libsim_a_OBJECTS) $(v850_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) v850/libsim.a
clean-checkPROGRAMS:
@list='$(check_PROGRAMS)'; test -n "$$list" || exit 0; \
frv/run$(EXEEXT): $(frv_run_OBJECTS) $(frv_run_DEPENDENCIES) $(EXTRA_frv_run_DEPENDENCIES) frv/$(am__dirstamp)
@rm -f frv/run$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(frv_run_OBJECTS) $(frv_run_LDADD) $(LIBS)
-ft32/$(am__dirstamp):
- @$(MKDIR_P) ft32
- @: > ft32/$(am__dirstamp)
ft32/run$(EXEEXT): $(ft32_run_OBJECTS) $(ft32_run_DEPENDENCIES) $(EXTRA_ft32_run_DEPENDENCIES) ft32/$(am__dirstamp)
@rm -f ft32/run$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(ft32_run_OBJECTS) $(ft32_run_LDADD) $(LIBS)
-h8300/$(am__dirstamp):
- @$(MKDIR_P) h8300
- @: > h8300/$(am__dirstamp)
h8300/run$(EXEEXT): $(h8300_run_OBJECTS) $(h8300_run_DEPENDENCIES) $(EXTRA_h8300_run_DEPENDENCIES) h8300/$(am__dirstamp)
@rm -f h8300/run$(EXEEXT)
igen/table$(EXEEXT): $(igen_table_OBJECTS) $(igen_table_DEPENDENCIES) $(EXTRA_igen_table_DEPENDENCIES) igen/$(am__dirstamp)
@rm -f igen/table$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(igen_table_OBJECTS) $(igen_table_LDADD) $(LIBS)
-iq2000/$(am__dirstamp):
- @$(MKDIR_P) iq2000
- @: > iq2000/$(am__dirstamp)
iq2000/run$(EXEEXT): $(iq2000_run_OBJECTS) $(iq2000_run_DEPENDENCIES) $(EXTRA_iq2000_run_DEPENDENCIES) iq2000/$(am__dirstamp)
@rm -f iq2000/run$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(iq2000_run_OBJECTS) $(iq2000_run_LDADD) $(LIBS)
-lm32/$(am__dirstamp):
- @$(MKDIR_P) lm32
- @: > lm32/$(am__dirstamp)
lm32/run$(EXEEXT): $(lm32_run_OBJECTS) $(lm32_run_DEPENDENCIES) $(EXTRA_lm32_run_DEPENDENCIES) lm32/$(am__dirstamp)
@rm -f lm32/run$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(lm32_run_OBJECTS) $(lm32_run_LDADD) $(LIBS)
-m32c/$(am__dirstamp):
- @$(MKDIR_P) m32c
- @: > m32c/$(am__dirstamp)
m32c/$(DEPDIR)/$(am__dirstamp):
@$(MKDIR_P) m32c/$(DEPDIR)
@: > m32c/$(DEPDIR)/$(am__dirstamp)
m32c/run$(EXEEXT): $(m32c_run_OBJECTS) $(m32c_run_DEPENDENCIES) $(EXTRA_m32c_run_DEPENDENCIES) m32c/$(am__dirstamp)
@rm -f m32c/run$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(m32c_run_OBJECTS) $(m32c_run_LDADD) $(LIBS)
-m32r/$(am__dirstamp):
- @$(MKDIR_P) m32r
- @: > m32r/$(am__dirstamp)
m32r/run$(EXEEXT): $(m32r_run_OBJECTS) $(m32r_run_DEPENDENCIES) $(EXTRA_m32r_run_DEPENDENCIES) m32r/$(am__dirstamp)
@rm -f m32r/run$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(m32r_run_OBJECTS) $(m32r_run_LDADD) $(LIBS)
-m68hc11/$(am__dirstamp):
- @$(MKDIR_P) m68hc11
- @: > m68hc11/$(am__dirstamp)
m68hc11/$(DEPDIR)/$(am__dirstamp):
@$(MKDIR_P) m68hc11/$(DEPDIR)
@: > m68hc11/$(DEPDIR)/$(am__dirstamp)
m68hc11/run$(EXEEXT): $(m68hc11_run_OBJECTS) $(m68hc11_run_DEPENDENCIES) $(EXTRA_m68hc11_run_DEPENDENCIES) m68hc11/$(am__dirstamp)
@rm -f m68hc11/run$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(m68hc11_run_OBJECTS) $(m68hc11_run_LDADD) $(LIBS)
-mcore/$(am__dirstamp):
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- @: > mcore/$(am__dirstamp)
mcore/run$(EXEEXT): $(mcore_run_OBJECTS) $(mcore_run_DEPENDENCIES) $(EXTRA_mcore_run_DEPENDENCIES) mcore/$(am__dirstamp)
@rm -f mcore/run$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(mcore_run_OBJECTS) $(mcore_run_LDADD) $(LIBS)
-microblaze/$(am__dirstamp):
- @$(MKDIR_P) microblaze
- @: > microblaze/$(am__dirstamp)
microblaze/run$(EXEEXT): $(microblaze_run_OBJECTS) $(microblaze_run_DEPENDENCIES) $(EXTRA_microblaze_run_DEPENDENCIES) microblaze/$(am__dirstamp)
@rm -f microblaze/run$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(microblaze_run_OBJECTS) $(microblaze_run_LDADD) $(LIBS)
-mips/$(am__dirstamp):
- @$(MKDIR_P) mips
- @: > mips/$(am__dirstamp)
mips/run$(EXEEXT): $(mips_run_OBJECTS) $(mips_run_DEPENDENCIES) $(EXTRA_mips_run_DEPENDENCIES) mips/$(am__dirstamp)
@rm -f mips/run$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(mips_run_OBJECTS) $(mips_run_LDADD) $(LIBS)
-mn10300/$(am__dirstamp):
- @$(MKDIR_P) mn10300
- @: > mn10300/$(am__dirstamp)
mn10300/run$(EXEEXT): $(mn10300_run_OBJECTS) $(mn10300_run_DEPENDENCIES) $(EXTRA_mn10300_run_DEPENDENCIES) mn10300/$(am__dirstamp)
@rm -f mn10300/run$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(mn10300_run_OBJECTS) $(mn10300_run_LDADD) $(LIBS)
-moxie/$(am__dirstamp):
- @$(MKDIR_P) moxie
- @: > moxie/$(am__dirstamp)
moxie/run$(EXEEXT): $(moxie_run_OBJECTS) $(moxie_run_DEPENDENCIES) $(EXTRA_moxie_run_DEPENDENCIES) moxie/$(am__dirstamp)
@rm -f moxie/run$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(moxie_run_OBJECTS) $(moxie_run_LDADD) $(LIBS)
-msp430/$(am__dirstamp):
- @$(MKDIR_P) msp430
- @: > msp430/$(am__dirstamp)
msp430/run$(EXEEXT): $(msp430_run_OBJECTS) $(msp430_run_DEPENDENCIES) $(EXTRA_msp430_run_DEPENDENCIES) msp430/$(am__dirstamp)
@rm -f msp430/run$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(msp430_run_OBJECTS) $(msp430_run_LDADD) $(LIBS)
-or1k/$(am__dirstamp):
- @$(MKDIR_P) or1k
- @: > or1k/$(am__dirstamp)
or1k/run$(EXEEXT): $(or1k_run_OBJECTS) $(or1k_run_DEPENDENCIES) $(EXTRA_or1k_run_DEPENDENCIES) or1k/$(am__dirstamp)
@rm -f or1k/run$(EXEEXT)
ppc/run$(EXEEXT): $(ppc_run_OBJECTS) $(ppc_run_DEPENDENCIES) $(EXTRA_ppc_run_DEPENDENCIES) ppc/$(am__dirstamp)
@rm -f ppc/run$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(ppc_run_OBJECTS) $(ppc_run_LDADD) $(LIBS)
-pru/$(am__dirstamp):
- @$(MKDIR_P) pru
- @: > pru/$(am__dirstamp)
pru/run$(EXEEXT): $(pru_run_OBJECTS) $(pru_run_DEPENDENCIES) $(EXTRA_pru_run_DEPENDENCIES) pru/$(am__dirstamp)
@rm -f pru/run$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(pru_run_OBJECTS) $(pru_run_LDADD) $(LIBS)
-riscv/$(am__dirstamp):
- @$(MKDIR_P) riscv
- @: > riscv/$(am__dirstamp)
riscv/run$(EXEEXT): $(riscv_run_OBJECTS) $(riscv_run_DEPENDENCIES) $(EXTRA_riscv_run_DEPENDENCIES) riscv/$(am__dirstamp)
@rm -f riscv/run$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(riscv_run_OBJECTS) $(riscv_run_LDADD) $(LIBS)
-rl78/$(am__dirstamp):
- @$(MKDIR_P) rl78
- @: > rl78/$(am__dirstamp)
rl78/run$(EXEEXT): $(rl78_run_OBJECTS) $(rl78_run_DEPENDENCIES) $(EXTRA_rl78_run_DEPENDENCIES) rl78/$(am__dirstamp)
@rm -f rl78/run$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(rl78_run_OBJECTS) $(rl78_run_LDADD) $(LIBS)
-rx/$(am__dirstamp):
- @$(MKDIR_P) rx
- @: > rx/$(am__dirstamp)
rx/run$(EXEEXT): $(rx_run_OBJECTS) $(rx_run_DEPENDENCIES) $(EXTRA_rx_run_DEPENDENCIES) rx/$(am__dirstamp)
@rm -f rx/run$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(rx_run_OBJECTS) $(rx_run_LDADD) $(LIBS)
-sh/$(am__dirstamp):
- @$(MKDIR_P) sh
- @: > sh/$(am__dirstamp)
sh/$(DEPDIR)/$(am__dirstamp):
@$(MKDIR_P) sh/$(DEPDIR)
@: > sh/$(DEPDIR)/$(am__dirstamp)
testsuite/common/$(DEPDIR)/$(am__dirstamp)
testsuite/common/fpu-tst.$(OBJEXT): testsuite/common/$(am__dirstamp) \
testsuite/common/$(DEPDIR)/$(am__dirstamp)
-v850/$(am__dirstamp):
- @$(MKDIR_P) v850
- @: > v850/$(am__dirstamp)
v850/run$(EXEEXT): $(v850_run_OBJECTS) $(v850_run_DEPENDENCIES) $(EXTRA_v850_run_DEPENDENCIES) v850/$(am__dirstamp)
@rm -f v850/run$(EXEEXT)
$(SHELL) $(srcroot)/move-if-change $@.tmp $(@D)/hw-config.h; \
touch $@
.PRECIOUS: %/stamp-hw
-%/modules.c:
- $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) GEN_MODULES_C_SRCS="$(GEN_MODULES_C_SRCS)" -C $(@D) $(@F)
+%/modules.c: %/stamp-modules ; @true
+%/stamp-modules: Makefile
+ $(AM_V_GEN)set -e; \
+ LANG=C ; export LANG; \
+ LC_ALL=C ; export LC_ALL; \
+ sed -n -e '/^sim_install_/{s/^\(sim_install_[a-z_0-9A-Z]*\).*/\1/;p}' $(GEN_MODULES_C_SRCS) | sort >$@.l-tmp; \
+ ( \
+ echo '/* Do not modify this file. */'; \
+ echo '/* It is created automatically by the Makefile. */'; \
+ echo '#include "libiberty.h"'; \
+ echo '#include "sim-module.h"'; \
+ sed -e 's:\(.*\):extern MODULE_INIT_FN \1;:' $@.l-tmp; \
+ echo 'MODULE_INSTALL_FN * const sim_modules_detected[] = {'; \
+ sed -e 's:\(.*\): \1,:' $@.l-tmp; \
+ echo '};'; \
+ echo 'const int sim_modules_detected_len = ARRAY_SIZE (sim_modules_detected);'; \
+ ) >$@.tmp; \
+ $(SHELL) $(srcroot)/move-if-change $@.tmp $(@D)/modules.c; \
+ rm -f $@.l-tmp; \
+ touch $@
+.PRECIOUS: %/stamp-modules
# Alias for developers.
@SIM_ENABLE_IGEN_TRUE@igen: $(IGEN)
$(AM_V_at)mv $@.tmp $@
@SIM_ENABLE_ARCH_aarch64_TRUE@$(aarch64_libsim_a_OBJECTS) $(aarch64_libsim_a_LIBADD): aarch64/hw-config.h
-@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64/%.o: aarch64/%.c
-@SIM_ENABLE_ARCH_aarch64_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
-
@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64/%.o: common/%.c
@SIM_ENABLE_ARCH_aarch64_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_arm_TRUE@$(arm_libsim_a_OBJECTS) $(arm_libsim_a_LIBADD): arm/hw-config.h
-@SIM_ENABLE_ARCH_arm_TRUE@arm/%.o: arm/%.c
-@SIM_ENABLE_ARCH_arm_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
-
@SIM_ENABLE_ARCH_arm_TRUE@arm/%.o: common/%.c
@SIM_ENABLE_ARCH_arm_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_avr_TRUE@$(avr_libsim_a_OBJECTS) $(avr_libsim_a_LIBADD): avr/hw-config.h
-@SIM_ENABLE_ARCH_avr_TRUE@avr/%.o: avr/%.c
-@SIM_ENABLE_ARCH_avr_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
-
@SIM_ENABLE_ARCH_avr_TRUE@avr/%.o: common/%.c
@SIM_ENABLE_ARCH_avr_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_bfin_TRUE@$(bfin_libsim_a_OBJECTS) $(bfin_libsim_a_LIBADD): bfin/hw-config.h
-@SIM_ENABLE_ARCH_bfin_TRUE@bfin/%.o: bfin/%.c
-@SIM_ENABLE_ARCH_bfin_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
-
@SIM_ENABLE_ARCH_bfin_TRUE@bfin/%.o: common/%.c
@SIM_ENABLE_ARCH_bfin_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_bfin_TRUE@ $(AM_V_at)touch $(srcdir)/bfin/linux-fixed-code.h
@SIM_ENABLE_ARCH_bpf_TRUE@$(bpf_libsim_a_OBJECTS) $(bpf_libsim_a_LIBADD): bpf/hw-config.h
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf/%.o: bpf/%.c
-@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
-
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/%.o: common/%.c
@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/modules.c: | $(bpf_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/sem-be.c bpf/decode-be.c bpf/decode-be.h: @CGEN_MAINT@ bpf/cgen-decode-be
@SIM_ENABLE_ARCH_cr16_TRUE@$(cr16_libsim_a_OBJECTS) $(cr16_libsim_a_LIBADD): cr16/hw-config.h
-@SIM_ENABLE_ARCH_cr16_TRUE@cr16/%.o: cr16/%.c
-@SIM_ENABLE_ARCH_cr16_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
-
@SIM_ENABLE_ARCH_cr16_TRUE@cr16/%.o: common/%.c
@SIM_ENABLE_ARCH_cr16_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_cr16_TRUE@cr16/modules.c: | $(cr16_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_cr16_TRUE@ $(AM_V_GEN)$< >$@
@SIM_ENABLE_ARCH_cris_TRUE@$(cris_libsim_a_OBJECTS) $(cris_libsim_a_LIBADD): cris/hw-config.h
-@SIM_ENABLE_ARCH_cris_TRUE@cris/%.o: cris/%.c
-@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
-
@SIM_ENABLE_ARCH_cris_TRUE@cris/%.o: common/%.c
@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_cris_TRUE@cris/modules.c: | $(cris_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_cris_TRUE@cris/cpuv32.h cris/cpuv32.c cris/semcrisv32f-switch.c cris/modelv32.c cris/decodev32.c cris/decodev32.h: @CGEN_MAINT@ cris/cgen-cpu-decode-v32f
@SIM_ENABLE_ARCH_d10v_TRUE@$(d10v_libsim_a_OBJECTS) $(d10v_libsim_a_LIBADD): d10v/hw-config.h
-@SIM_ENABLE_ARCH_d10v_TRUE@d10v/%.o: d10v/%.c
-@SIM_ENABLE_ARCH_d10v_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
-
@SIM_ENABLE_ARCH_d10v_TRUE@d10v/%.o: common/%.c
@SIM_ENABLE_ARCH_d10v_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_d10v_TRUE@d10v/modules.c: | $(d10v_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_d10v_TRUE@ $(AM_V_GEN)$< >$@
@SIM_ENABLE_ARCH_erc32_TRUE@$(erc32_libsim_a_OBJECTS) $(erc32_libsim_a_LIBADD): erc32/hw-config.h
-@SIM_ENABLE_ARCH_erc32_TRUE@erc32/%.o: erc32/%.c
-@SIM_ENABLE_ARCH_erc32_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
-
@SIM_ENABLE_ARCH_erc32_TRUE@erc32/%.o: common/%.c
@SIM_ENABLE_ARCH_erc32_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_erc32_TRUE@ rm -f $(DESTDIR)$(bindir)/sis
@SIM_ENABLE_ARCH_examples_TRUE@$(example_synacor_libsim_a_OBJECTS) $(example_synacor_libsim_a_LIBADD): example-synacor/hw-config.h
-@SIM_ENABLE_ARCH_examples_TRUE@example-synacor/%.o: example-synacor/%.c
-@SIM_ENABLE_ARCH_examples_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
-
@SIM_ENABLE_ARCH_examples_TRUE@example-synacor/%.o: common/%.c
@SIM_ENABLE_ARCH_examples_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_frv_TRUE@$(frv_libsim_a_OBJECTS) $(frv_libsim_a_LIBADD): frv/hw-config.h
-@SIM_ENABLE_ARCH_frv_TRUE@frv/%.o: frv/%.c
-@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
-
@SIM_ENABLE_ARCH_frv_TRUE@frv/%.o: common/%.c
@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_frv_TRUE@frv/modules.c: | $(frv_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_frv_TRUE@frv/cgen-cpu-decode:
@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_GEN)cpu=frvbf mach=frv,fr550,fr500,fr450,fr400,tomcat,simple FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" EXTRAFILES="$(CGEN_CPU_SEM)"; $(CGEN_GEN_CPU_DECODE)
@SIM_ENABLE_ARCH_frv_TRUE@frv/cpu.h frv/sem.c frv/model.c frv/decode.c frv/decode.h: @CGEN_MAINT@ frv/cgen-cpu-decode
+@SIM_ENABLE_ARCH_ft32_TRUE@$(ft32_libsim_a_OBJECTS) $(ft32_libsim_a_LIBADD): ft32/hw-config.h
+
+@SIM_ENABLE_ARCH_ft32_TRUE@ft32/%.o: common/%.c
+@SIM_ENABLE_ARCH_ft32_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+@SIM_ENABLE_ARCH_h8300_TRUE@$(h8300_libsim_a_OBJECTS) $(h8300_libsim_a_LIBADD): h8300/hw-config.h
+
+@SIM_ENABLE_ARCH_h8300_TRUE@h8300/%.o: common/%.c
+@SIM_ENABLE_ARCH_h8300_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+@SIM_ENABLE_ARCH_iq2000_TRUE@$(iq2000_libsim_a_OBJECTS) $(iq2000_libsim_a_LIBADD): iq2000/hw-config.h
+
+@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/%.o: common/%.c
+@SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/modules.c: | $(iq2000_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/mloop.c iq2000/eng.h: iq2000/stamp-mloop ; @true
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/cgen-cpu-decode:
@SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_GEN)cpu=iq2000bf mach=iq2000 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/cpu.h iq2000/sem.c iq2000/sem-switch.c iq2000/model.c iq2000/decode.c iq2000/decode.h: @CGEN_MAINT@ iq2000/cgen-cpu-decode
+@SIM_ENABLE_ARCH_lm32_TRUE@$(lm32_libsim_a_OBJECTS) $(lm32_libsim_a_LIBADD): lm32/hw-config.h
+
+@SIM_ENABLE_ARCH_lm32_TRUE@lm32/%.o: common/%.c
+@SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_lm32_TRUE@lm32/modules.c: | $(lm32_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_lm32_TRUE@lm32/mloop.c lm32/eng.h: lm32/stamp-mloop ; @true
@SIM_ENABLE_ARCH_lm32_TRUE@lm32/cgen-cpu-decode:
@SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_GEN)cpu=lm32bf mach=lm32 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
@SIM_ENABLE_ARCH_lm32_TRUE@lm32/cpu.h lm32/sem.c lm32/sem-switch.c lm32/model.c lm32/decode.c lm32/decode.h: @CGEN_MAINT@ lm32/cgen-cpu-decode
+@SIM_ENABLE_ARCH_m32c_TRUE@$(m32c_libsim_a_OBJECTS) $(m32c_libsim_a_LIBADD): m32c/hw-config.h
-@SIM_ENABLE_ARCH_m32c_TRUE@m32c/%.o: m32c/%.c | m32c/libsim.a $(SIM_ALL_RECURSIVE_DEPS)
-@SIM_ENABLE_ARCH_m32c_TRUE@ $(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+@SIM_ENABLE_ARCH_m32c_TRUE@m32c/%.o: common/%.c
+@SIM_ENABLE_ARCH_m32c_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_m32c_TRUE@m32c/modules.c: | $(m32c_BUILD_OUTPUTS)
# These rules are copied from automake, but tweaked to use FOR_BUILD variables.
@SIM_ENABLE_ARCH_m32c_TRUE@m32c/r8c.c: m32c/r8c.opc m32c/opc2c$(EXEEXT)
@SIM_ENABLE_ARCH_m32c_TRUE@ $(AM_V_GEN)$(m32c_OPC2C_RUN) -l $@.log $< > $@.tmp
@SIM_ENABLE_ARCH_m32c_TRUE@ $(AM_V_at)mv $@.tmp $@
+@SIM_ENABLE_ARCH_m32r_TRUE@$(m32r_libsim_a_OBJECTS) $(m32r_libsim_a_LIBADD): m32r/hw-config.h
+
+@SIM_ENABLE_ARCH_m32r_TRUE@m32r/%.o: common/%.c
+@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/modules.c: | $(m32r_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/mloop.c m32r/eng.h: m32r/stamp-mloop ; @true
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cgen-cpu-decode-2:
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)cpu=m32r2f mach=m32r2 SUFFIX=2 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cpu2.h m32r/sem2-switch.c m32r/model2.c m32r/decode2.c m32r/decode2.h: @CGEN_MAINT@ m32r/cgen-cpu-decode-2
+@SIM_ENABLE_ARCH_m68hc11_TRUE@$(m68hc11_libsim_a_OBJECTS) $(m68hc11_libsim_a_LIBADD): m68hc11/hw-config.h
+
+@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/%.o: common/%.c
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/modules.c: | $(m68hc11_BUILD_OUTPUTS)
# These rules are copied from automake, but tweaked to use FOR_BUILD variables.
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/m68hc12int.c: m68hc11/gencode$(EXEEXT)
@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(AM_V_GEN)$< -m6812 >$@
+@SIM_ENABLE_ARCH_mcore_TRUE@$(mcore_libsim_a_OBJECTS) $(mcore_libsim_a_LIBADD): mcore/hw-config.h
+
+@SIM_ENABLE_ARCH_mcore_TRUE@mcore/%.o: common/%.c
+@SIM_ENABLE_ARCH_mcore_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+@SIM_ENABLE_ARCH_microblaze_TRUE@$(microblaze_libsim_a_OBJECTS) $(microblaze_libsim_a_LIBADD): microblaze/hw-config.h
+
+@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze/%.o: common/%.c
+@SIM_ENABLE_ARCH_microblaze_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+@SIM_ENABLE_ARCH_mips_TRUE@$(mips_libsim_a_OBJECTS) $(mips_libsim_a_LIBADD): mips/hw-config.h
+
+@SIM_ENABLE_ARCH_mips_TRUE@mips/%.o: common/%.c
+@SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_mips_TRUE@mips/modules.c: | $(mips_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_mips_TRUE@$(mips_BUILT_SRC_FROM_IGEN_ITABLE): mips/stamp-igen-itable
@SIM_ENABLE_ARCH_mips_TRUE@ esac \
@SIM_ENABLE_ARCH_mips_TRUE@ done
@SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_at)touch $@
+@SIM_ENABLE_ARCH_mn10300_TRUE@$(mn10300_libsim_a_OBJECTS) $(mn10300_libsim_a_LIBADD): mn10300/hw-config.h
+
+@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300/%.o: mn10300/%.c
+@SIM_ENABLE_ARCH_mn10300_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+
+@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300/%.o: common/%.c
+@SIM_ENABLE_ARCH_mn10300_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300/modules.c: | $(mn10300_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_mn10300_TRUE@$(mn10300_BUILT_SRC_FROM_IGEN): mn10300/stamp-igen
@SIM_ENABLE_ARCH_mn10300_TRUE@ -n engine.c -e mn10300/engine.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@ -n irun.c -r mn10300/irun.c
@SIM_ENABLE_ARCH_mn10300_TRUE@ $(AM_V_at)touch $@
+@SIM_ENABLE_ARCH_moxie_TRUE@$(moxie_libsim_a_OBJECTS) $(moxie_libsim_a_LIBADD): moxie/hw-config.h
+
+@SIM_ENABLE_ARCH_moxie_TRUE@moxie/%.o: moxie/%.c
+@SIM_ENABLE_ARCH_moxie_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+
+@SIM_ENABLE_ARCH_moxie_TRUE@moxie/%.o: common/%.c
+@SIM_ENABLE_ARCH_moxie_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_moxie_TRUE@moxie/moxie-gdb.dtb: @MAINT@ moxie/moxie-gdb.dts moxie/$(am__dirstamp)
@SIM_ENABLE_ARCH_moxie_TRUE@ $(AM_V_GEN) \
@SIM_ENABLE_ARCH_moxie_TRUE@ echo "tree compiler tool (dtc) is missing. Install the tool to "; \
@SIM_ENABLE_ARCH_moxie_TRUE@ echo "update the device tree blob."; \
@SIM_ENABLE_ARCH_moxie_TRUE@ fi
+@SIM_ENABLE_ARCH_msp430_TRUE@$(msp430_libsim_a_OBJECTS) $(msp430_libsim_a_LIBADD): msp430/hw-config.h
+
+@SIM_ENABLE_ARCH_msp430_TRUE@msp430/%.o: msp430/%.c
+@SIM_ENABLE_ARCH_msp430_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+
+@SIM_ENABLE_ARCH_msp430_TRUE@msp430/%.o: common/%.c
+@SIM_ENABLE_ARCH_msp430_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+@SIM_ENABLE_ARCH_or1k_TRUE@$(or1k_libsim_a_OBJECTS) $(or1k_libsim_a_LIBADD): or1k/hw-config.h
+
+@SIM_ENABLE_ARCH_or1k_TRUE@or1k/%.o: or1k/%.c
+@SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+
+@SIM_ENABLE_ARCH_or1k_TRUE@or1k/%.o: common/%.c
+@SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_or1k_TRUE@or1k/modules.c: | $(or1k_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_or1k_TRUE@or1k/mloop.c or1k/eng.h: or1k/stamp-mloop ; @true
@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_GEN)$(srcdir)/ppc/spreg-gen.py --header $@.tmp
@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change $@.tmp $(srcdir)/ppc/spreg.h
@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)touch $(srcdir)/ppc/spreg.h
+@SIM_ENABLE_ARCH_pru_TRUE@$(pru_libsim_a_OBJECTS) $(pru_libsim_a_LIBADD): pru/hw-config.h
+
+@SIM_ENABLE_ARCH_pru_TRUE@pru/%.o: pru/%.c
+@SIM_ENABLE_ARCH_pru_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+
+@SIM_ENABLE_ARCH_pru_TRUE@pru/%.o: common/%.c
+@SIM_ENABLE_ARCH_pru_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+@SIM_ENABLE_ARCH_riscv_TRUE@$(riscv_libsim_a_OBJECTS) $(riscv_libsim_a_LIBADD): riscv/hw-config.h
+
+@SIM_ENABLE_ARCH_riscv_TRUE@riscv/%.o: riscv/%.c
+@SIM_ENABLE_ARCH_riscv_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+
+@SIM_ENABLE_ARCH_riscv_TRUE@riscv/%.o: common/%.c
+@SIM_ENABLE_ARCH_riscv_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+@SIM_ENABLE_ARCH_rl78_TRUE@$(rl78_libsim_a_OBJECTS) $(rl78_libsim_a_LIBADD): rl78/hw-config.h
+
+@SIM_ENABLE_ARCH_rl78_TRUE@rl78/%.o: rl78/%.c
+@SIM_ENABLE_ARCH_rl78_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+
+@SIM_ENABLE_ARCH_rl78_TRUE@rl78/%.o: common/%.c
+@SIM_ENABLE_ARCH_rl78_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+@SIM_ENABLE_ARCH_rx_TRUE@$(rx_libsim_a_OBJECTS) $(rx_libsim_a_LIBADD): rx/hw-config.h
-@SIM_ENABLE_ARCH_rl78_TRUE@rl78/%.o: rl78/%.c | rl78/libsim.a $(SIM_ALL_RECURSIVE_DEPS)
-@SIM_ENABLE_ARCH_rl78_TRUE@ $(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+@SIM_ENABLE_ARCH_rx_TRUE@rx/%.o: rx/%.c
+@SIM_ENABLE_ARCH_rx_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
-@SIM_ENABLE_ARCH_rx_TRUE@rx/%.o: rx/%.c | rx/libsim.a $(SIM_ALL_RECURSIVE_DEPS)
-@SIM_ENABLE_ARCH_rx_TRUE@ $(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+@SIM_ENABLE_ARCH_rx_TRUE@rx/%.o: common/%.c
+@SIM_ENABLE_ARCH_rx_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+@SIM_ENABLE_ARCH_sh_TRUE@$(sh_libsim_a_OBJECTS) $(sh_libsim_a_LIBADD): sh/hw-config.h
+
+@SIM_ENABLE_ARCH_sh_TRUE@sh/%.o: sh/%.c
+@SIM_ENABLE_ARCH_sh_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+
+@SIM_ENABLE_ARCH_sh_TRUE@sh/%.o: common/%.c
+@SIM_ENABLE_ARCH_sh_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_sh_TRUE@sh/modules.c: | $(sh_BUILD_OUTPUTS)
# These rules are copied from automake, but tweaked to use FOR_BUILD variables.
@SIM_ENABLE_ARCH_sh_TRUE@sh/table.c: sh/gencode$(EXEEXT)
@SIM_ENABLE_ARCH_sh_TRUE@ $(AM_V_GEN)$< -s >$@
+@SIM_ENABLE_ARCH_v850_TRUE@$(v850_libsim_a_OBJECTS) $(v850_libsim_a_LIBADD): v850/hw-config.h
+
+@SIM_ENABLE_ARCH_v850_TRUE@v850/%.o: v850/%.c
+@SIM_ENABLE_ARCH_v850_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+
+@SIM_ENABLE_ARCH_v850_TRUE@v850/%.o: common/%.c
+@SIM_ENABLE_ARCH_v850_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_v850_TRUE@v850/modules.c: | $(v850_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_v850_TRUE@$(v850_BUILT_SRC_FROM_IGEN): v850/stamp-igen
@SIM_ENABLE_ARCH_v850_TRUE@ -n irun.c -r v850/irun.c
@SIM_ENABLE_ARCH_v850_TRUE@ $(AM_V_at)touch $@
-%/libsim.a: | $(SIM_ALL_RECURSIVE_DEPS)
- $(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
-
-%/nrun.o: common/nrun.c | %/libsim.a $(SIM_ALL_RECURSIVE_DEPS)
- $(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
-
all-recursive: $(SIM_ALL_RECURSIVE_DEPS)
install-data-local: installdirs $(SIM_INSTALL_DATA_LOCAL_DEPS)
projects / binutils-gdb.git / blobdiff