Index: sim/frv/ChangeLog

[binutils-gdb.git] / sim / common / sim-fpu.c

diff --git a/sim/common/sim-fpu.c b/sim/common/sim-fpu.c
index 99381e06b179ad013b019859b61c442fbca2f5df..845248adb590e9b5619348ad511855c15535a69c 100644 (file)
--- a/sim/common/sim-fpu.c
+++ b/sim/common/sim-fpu.c
@@ -2,7 +2,7 @@
    of the floating point routines in libgcc1.c for targets without
    hardware floating point.  */
 
-/* Copyright (C) 1994,1997-1998 Free Software Foundation, Inc.
+/* Copyright 1994, 1997, 1998, 2003 Free Software Foundation, Inc.
 
 This file is free software; you can redistribute it and/or modify it
 under the terms of the GNU General Public License as published by the
@@ -51,25 +51,30 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
 #include "sim-assert.h"
 
 
-/* Debugging support. */
+/* Debugging support. 
+   If digits is -1, then print all digits.  */
 
 static void
 print_bits (unsigned64 x,
            int msbit,
+           int digits,
            sim_fpu_print_func print,
            void *arg)
 {
   unsigned64 bit = LSBIT64 (msbit);
   int i = 4;
-  while (bit)
+  while (bit && digits)
     {
       if (i == 0)
        print (arg, ",");
+
       if ((x & bit))
        print (arg, "1");
       else
        print (arg, "0");
       bit >>= 1;
+
+      if (digits > 0) digits--;
       i = (i + 1) % 4;
     }
 }
@@ -325,6 +330,7 @@ unpack_fpu (sim_fpu *dst, unsigned64 packed, int is_double)
          /* tastes like zero */
          dst->class = sim_fpu_class_zero;
          dst->sign = sign;
+         dst->normal_exp = 0;
        }
       else
        {
@@ -515,6 +521,7 @@ i2fpu (sim_fpu *f, signed64 i, int is_64bit)
     {
       f->class = sim_fpu_class_zero;
       f->sign = 0;
+      f->normal_exp = 0;
     }
   else
     {
@@ -643,6 +650,7 @@ u2fpu (sim_fpu *f, unsigned64 u, int is_64bit)
     {
       f->class = sim_fpu_class_zero;
       f->sign = 0;
+      f->normal_exp = 0;
     }
   else
     {
@@ -1375,14 +1383,6 @@ sim_fpu_mul (sim_fpu *f,
     ASSERT (high >= LSBIT64 ((NR_FRAC_GUARD * 2) - 64));
     ASSERT (LSBIT64 (((NR_FRAC_GUARD + 1) * 2) - 64) < IMPLICIT_1);
 
-#if 0
-    printf ("\n");
-    print_bits (high, 63, (sim_fpu_print_func*)fprintf, stdout);
-    printf (";");
-    print_bits (low, 63, (sim_fpu_print_func*)fprintf, stdout);
-    printf ("\n");
-#endif
-
     /* normalize */
     do
       {
@@ -1394,13 +1394,6 @@ sim_fpu_mul (sim_fpu *f,
       }
     while (high < IMPLICIT_1);
 
-#if 0
-    print_bits (high, 63, (sim_fpu_print_func*)fprintf, stdout);
-    printf (";");
-    print_bits (low, 63, (sim_fpu_print_func*)fprintf, stdout);
-    printf ("\n");
-#endif
-
     ASSERT (high >= IMPLICIT_1 && high < IMPLICIT_2);
     if (low != 0)
       {
@@ -1530,16 +1523,6 @@ sim_fpu_div (sim_fpu *f,
        numerator <<= 1;
       }
 
-#if 0
-    printf ("\n");
-    print_bits (quotient, 63, (sim_fpu_print_func*)fprintf, stdout);
-    printf ("\n");
-    print_bits (numerator, 63, (sim_fpu_print_func*)fprintf, stdout);
-    printf ("\n");
-    print_bits (denominator, 63, (sim_fpu_print_func*)fprintf, stdout);
-    printf ("\n");
-#endif
-
     /* discard (but save) the extra bits */
     if ((quotient & LSMASK64 (NR_SPARE -1, 0)))
       quotient = (quotient >> NR_SPARE) | 1;
@@ -1771,33 +1754,7 @@ INLINE_SIM_FPU (int)
 sim_fpu_inv (sim_fpu *f,
             const sim_fpu *r)
 {
-  if (sim_fpu_is_snan (r))
-    {
-      *f = *r;
-      f->class = sim_fpu_class_qnan;
-      return sim_fpu_status_invalid_snan;
-    }
-  if (sim_fpu_is_qnan (r))
-    {
-      *f = *r;
-      f->class = sim_fpu_class_qnan;
-      return 0;
-    }
-  if (sim_fpu_is_infinity (r))
-    {
-      *f = sim_fpu_zero;
-      f->sign = r->sign;
-      return 0;
-    }
-  if (sim_fpu_is_zero (r))
-    {
-      f->class = sim_fpu_class_infinity;
-      f->sign = r->sign;
-      return sim_fpu_status_invalid_div0;
-    }
-  *f = *r;
-  f->normal_exp = - r->normal_exp;
-  return 0;
+  return sim_fpu_div (f, &sim_fpu_one, r);
 }
 
 
@@ -1819,6 +1776,7 @@ sim_fpu_sqrt (sim_fpu *f,
     {
       f->class = sim_fpu_class_zero;
       f->sign = r->sign;
+      f->normal_exp = 0;
       return 0;
     }
   if (sim_fpu_is_infinity (r))
@@ -2230,6 +2188,22 @@ sim_fpu_exp (const sim_fpu *d)
 }
 
 
+INLINE_SIM_FPU (unsigned64)
+sim_fpu_fraction (const sim_fpu *d)
+{
+  return d->fraction;
+}
+
+
+INLINE_SIM_FPU (unsigned64)
+sim_fpu_guard (const sim_fpu *d, int is_double)
+{
+  unsigned64 rv;
+  unsigned64 guardmask = LSMASK64 (NR_GUARDS - 1, 0);
+  rv = (d->fraction & guardmask) >> NR_PAD;
+  return rv;
+}
+
 
 INLINE_SIM_FPU (int)
 sim_fpu_is (const sim_fpu *d)
@@ -2456,10 +2430,10 @@ const sim_fpu sim_fpu_qnan = {
   sim_fpu_class_qnan,
 };
 const sim_fpu sim_fpu_one = {
-  sim_fpu_class_number, 0, IMPLICIT_1, 1
+  sim_fpu_class_number, 0, IMPLICIT_1, 0
 };
 const sim_fpu sim_fpu_two = {
-  sim_fpu_class_number, 0, IMPLICIT_1, 2
+  sim_fpu_class_number, 0, IMPLICIT_1, 1
 };
 const sim_fpu sim_fpu_max32 = {
   sim_fpu_class_number, 0, LSMASK64 (NR_FRAC_GUARD, NR_GUARDS32), NORMAL_EXPMAX32
@@ -2476,18 +2450,27 @@ INLINE_SIM_FPU (void)
 sim_fpu_print_fpu (const sim_fpu *f,
                   sim_fpu_print_func *print,
                   void *arg)
+{
+  sim_fpu_printn_fpu (f, print, -1, arg);
+}
+
+INLINE_SIM_FPU (void)
+sim_fpu_printn_fpu (const sim_fpu *f,
+                  sim_fpu_print_func *print,
+                  int digits,
+                  void *arg)
 {
   print (arg, "%s", f->sign ? "-" : "+");
   switch (f->class)
     {
     case sim_fpu_class_qnan:
       print (arg, "0.");
-      print_bits (f->fraction, NR_FRAC_GUARD - 1, print, arg);
+      print_bits (f->fraction, NR_FRAC_GUARD - 1, digits, print, arg);
       print (arg, "*QuietNaN");
       break;
     case sim_fpu_class_snan:
       print (arg, "0.");
-      print_bits (f->fraction, NR_FRAC_GUARD - 1, print, arg);
+      print_bits (f->fraction, NR_FRAC_GUARD - 1, digits, print, arg);
       print (arg, "*SignalNaN");
       break;
     case sim_fpu_class_zero:
@@ -2499,8 +2482,8 @@ sim_fpu_print_fpu (const sim_fpu *f,
     case sim_fpu_class_number:
     case sim_fpu_class_denorm:
       print (arg, "1.");
-      print_bits (f->fraction, NR_FRAC_GUARD - 1, print, arg);
-      print (arg, "*2^%+-5d", f->normal_exp);
+      print_bits (f->fraction, NR_FRAC_GUARD - 1, digits, print, arg);
+      print (arg, "*2^%+d", f->normal_exp);
       ASSERT (f->fraction >= IMPLICIT_1);
       ASSERT (f->fraction < IMPLICIT_2);
     }