/* CRIS base simulator support code
- Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009, 2010
- Free Software Foundation, Inc.
+ Copyright (C) 2004-2022 Free Software Foundation, Inc.
Contributed by Axis Communications.
This file is part of the GNU simulators.
/* The infrastructure is based on that of i960.c. */
+/* This must come before any other includes. */
+#include "defs.h"
+
#define WANT_CPU
#include "sim-main.h"
#include "cgen-mem.h"
#include "cgen-ops.h"
+#include <stdlib.h>
+
#define MY(f) XCONCAT3(crisv,BASENUM,f)
/* Dispatcher for break insn. */
{
int i;
char flags[7];
- unsigned64 cycle_count;
+ uint64_t cycle_count;
SIM_DESC sd = CPU_STATE (current_cpu);
#endif
}
+#if 0
/* Initialize cycle counting for an insn.
FIRST_P is non-zero if this is the first insn in a set of parallel
insns. */
abort ();
}
-#if 0
void
MY (f_model_record_cycles) (SIM_CPU *current_cpu, unsigned long cycles)
{
\f
/* Set the thread register contents. */
-void
+static void
MY (set_target_thread_data) (SIM_CPU *current_cpu, USI val)
{
(CPU (XCONCAT2 (h_sr_v, BASENUM) [CRIS_TLS_REGISTER])) = val;
/* Create the context for a thread. */
-void *
+static void *
MY (make_thread_cpu_data) (SIM_CPU *current_cpu, void *context)
{
void *info = xmalloc (current_cpu->thread_cpu_data_size);