sim: enable hardware support by default

[binutils-gdb.git] / sim / frv / Makefile.in

diff --git a/sim/frv/Makefile.in b/sim/frv/Makefile.in
index e936c889eff0db66ad51d20585bee8088657f040..87599614020467f152d6676998211d623e2bbf33 100644 (file)
--- a/sim/frv/Makefile.in
+++ b/sim/frv/Makefile.in
@@ -1,10 +1,10 @@
 # Makefile template for Configure for the frv simulator
-# Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+# Copyright (C) 1998-2021 Free Software Foundation, Inc.
 # Contributed by Red Hat.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
+# the Free Software Foundation; either version 3 of the License, or
 # (at your option) any later version.
 #
 # This program is distributed in the hope that it will be useful,
@@ -12,43 +12,32 @@
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
 #
-# You should have received a copy of the GNU General Public License along
-# with this program; if not, write to the Free Software Foundation, Inc.,
-# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
 
 ## COMMON_PRE_CONFIG_FRAG
 
 FRV_OBJS = frv.o cpu.o decode.o sem.o model.o mloop.o cgen-par.o
 
-CONFIG_DEVICES = dv-sockser.o
-CONFIG_DEVICES =
-
 SIM_OBJS = \
        $(SIM_NEW_COMMON_OBJS) \
-       sim-cpu.o \
-       sim-hload.o \
-       sim-hrw.o \
-       sim-model.o \
-       sim-reg.o \
        cgen-utils.o cgen-trace.o cgen-scache.o cgen-fpu.o cgen-accfp.o \
-       cgen-run.o sim-reason.o sim-engine.o sim-stop.o \
+       cgen-run.o \
        sim-if.o arch.o \
        $(FRV_OBJS) \
        traps.o interrupts.o memory.o cache.o pipeline.o \
-       profile.o profile-fr400.o profile-fr500.o options.o \
-       devices.o reset.o registers.o \
-       $(CONFIG_DEVICES)
+       profile.o profile-fr400.o profile-fr450.o profile-fr500.o profile-fr550.o options.o \
+       reset.o registers.o
 
 # Extra headers included by sim-main.h.
 SIM_EXTRA_DEPS = \
        $(CGEN_INCLUDE_DEPS) \
        arch.h cpuall.h frv-sim.h $(srcdir)/../../opcodes/frv-desc.h cache.h \
-       registers.h profile.h \
+       registers.h profile.h eng.h \
        $(sim-options_h)
 
 SIM_EXTRA_CFLAGS = @sim_trapdump@
 
-SIM_RUN_OBJS = nrun.o
 SIM_EXTRA_CLEAN = frv-clean
 
 # This selects the frv newlib/libgloss syscall definitions.
@@ -58,10 +47,6 @@ NL_TARGET = -DNL_TARGET_frv
 
 arch = frv
 
-arch.o: arch.c $(SIM_MAIN_DEPS)
-
-devices.o: devices.c $(SIM_MAIN_DEPS)
-
 # FRV objs
 
 FRVBF_INCLUDE_DEPS = \
@@ -69,36 +54,15 @@ FRVBF_INCLUDE_DEPS = \
        $(SIM_EXTRA_DEPS) \
        cpu.h decode.h eng.h
 
-frv.o: frv.c $(FRVBF_INCLUDE_DEPS)
-traps.o: traps.c $(FRVBF_INCLUDE_DEPS)
-pipeline.o: pipeline.c $(FRVBF_INCLUDE_DEPS)
-interrupts.o: interrupts.c $(FRVBF_INCLUDE_DEPS)
-memory.o: memory.c $(FRVBF_INCLUDE_DEPS)
-cache.o: cache.c $(FRVBF_INCLUDE_DEPS)
-options.o: options.c $(FRVBF_INCLUDE_DEPS)
-reset.o: reset.c $(FRVBF_INCLUDE_DEPS)
-registers.o: registers.c $(FRVBF_INCLUDE_DEPS)
-profile.o: profile.c profile-fr400.h profile-fr500.h $(FRVBF_INCLUDE_DEPS)
-profile-fr400.o: profile-fr400.c profile-fr400.h $(FRVBF_INCLUDE_DEPS)
-profile-fr500.o: profile-fr500.c profile-fr500.h $(FRVBF_INCLUDE_DEPS)
-sim-if.o: sim-if.c $(FRVBF_INCLUDE_DEPS) $(srcdir)/../common/sim-core.h eng.h
-
-
 # FIXME: Use of `mono' is wip.
 mloop.c eng.h: stamp-mloop
 stamp-mloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
-       $(SHELL) $(srccom)/genmloop.sh \
+       $(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
                -mono -scache -parallel-generic-write -parallel-only \
                -cpu frvbf -infile $(srcdir)/mloop.in
        $(SHELL) $(srcroot)/move-if-change eng.hin eng.h
        $(SHELL) $(srcroot)/move-if-change mloop.cin mloop.c
        touch stamp-mloop
-mloop.o: mloop.c $(FRVBF_INCLUDE_DEPS)
-
-cpu.o: cpu.c $(FRVBF_INCLUDE_DEPS)
-decode.o: decode.c $(FRVBF_INCLUDE_DEPS)
-sem.o: sem.c $(FRVBF_INCLUDE_DEPS)
-model.o: model.c $(FRVBF_INCLUDE_DEPS)
 
 frv-clean:
        rm -f mloop.c eng.h stamp-mloop
@@ -120,7 +84,7 @@ arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
 
 stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(srcdir)/../../cpu/frv.cpu
        $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
-         cpu=frvbf mach=frv,fr500,fr400,tomcat,simple SUFFIX= \
+         cpu=frvbf mach=frv,fr550,fr500,fr450,fr400,tomcat,simple SUFFIX= \
          archfile=$(srcdir)/../../cpu/frv.cpu \
          FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" \
          EXTRAFILES="$(CGEN_CPU_SEM)"