PR29482 - strip: heap-buffer-overflow

[binutils-gdb.git] / sim / frv / frv-sim.h

diff --git a/sim/frv/frv-sim.h b/sim/frv/frv-sim.h
index 00717d2bccb96225f09fe0e8616090b0dbc4d4e1..1d546f324e7c226c02b2f3b31f2ccd23fea3e459 100644 (file)
--- a/sim/frv/frv-sim.h
+++ b/sim/frv/frv-sim.h
@@ -1,6 +1,5 @@
 /* collection of junk waiting time to sort out
-   Copyright (C) 1998, 1999, 2000, 2001, 2003, 2007, 2008, 2009, 2010
-   Free Software Foundation, Inc.
+   Copyright (C) 1998-2022 Free Software Foundation, Inc.
    Contributed by Red Hat
 
 This file is part of the GNU Simulators.
@@ -123,24 +122,6 @@ extern void frvbf_force_update (SIM_CPU *);
 /* Hardware/device support.
    ??? Will eventually want to move device stuff to config files.  */
 
-/* Support for the MCCR register (Cache Control Register) is needed in order
-   for overlays to work correctly with the scache: cached instructions need
-   to be flushed when the instruction space is changed at runtime.  */
-
-/* These were just copied from another port and are necessary to build, but
-   but don't appear to be used.  */
-#define MCCR_ADDR 0xffffffff
-#define MCCR_CP 0x80
-/* not supported */
-#define MCCR_CM0 2
-#define MCCR_CM1 1
-
-/* sim_core_attach device argument.  */
-extern device frv_devices;
-
-/* FIXME: Temporary, until device support ready.  */
-struct _device { int foo; };
-
 /* maintain the address of the start of the previous VLIW insn sequence.  */
 extern IADDR previous_vliw_pc;
 extern CGEN_ATTR_VALUE_ENUM_TYPE frv_current_fm_slot;
@@ -660,6 +641,7 @@ void frvbf_media_register_not_aligned (SIM_CPU *);
 void frvbf_media_acc_not_aligned (SIM_CPU *);
 void frvbf_media_cr_not_aligned (SIM_CPU *);
 void frvbf_media_overflow (SIM_CPU *, int);
+SI frvbf_media_average (SIM_CPU *, SI, SI);
 
 /* Functions for queuing and processing interrupts.  */
 struct frv_interrupt_queue_element *
@@ -698,6 +680,9 @@ frv_queue_mem_address_not_aligned_interrupt (SIM_CPU *, USI);
 struct frv_interrupt_queue_element *
 frv_queue_data_access_error_interrupt (SIM_CPU *, USI);
 
+struct frv_interrupt_queue_element *
+frv_queue_data_access_exception_interrupt (SIM_CPU *);
+
 struct frv_interrupt_queue_element *
 frv_queue_instruction_access_error_interrupt (SIM_CPU *);
 
@@ -709,6 +694,9 @@ frv_queue_fp_exception_interrupt (SIM_CPU *, struct frv_fp_exception_info *);
 
 enum frv_dtt frvbf_division_exception (SIM_CPU *, enum frv_dtt, int, int);
 
+struct frv_interrupt_queue_element *
+frv_queue_division_exception_interrupt (SIM_CPU *, enum frv_dtt);
+
 struct frv_interrupt_queue_element *
 frv_queue_interrupt (SIM_CPU *, enum frv_interrupt_kind);
 
@@ -864,6 +852,8 @@ USI frv_rett (SIM_CPU *current_cpu, PCADDR pc, BI debug_field);
 
 BI   frvbf_check_non_excepting_load (SIM_CPU *, SI, SI, SI, SI, QI, BI);
 void frvbf_check_recovering_store (SIM_CPU *, PCADDR, SI, int, int);
+SI   frvbf_check_acc_range (SIM_CPU *, SI);
+void frvbf_check_swap_address (SIM_CPU *, SI);
 
 void frvbf_clear_ne_flags (SIM_CPU *, SI, BI);
 void frvbf_commit (SIM_CPU *, SI, BI);
@@ -883,12 +873,12 @@ extern int insns_in_slot[];
 #define INSNS_IN_SLOT(slot) (insns_in_slot[slot])
     
 /* Multiple loads and stores.  */
-void frvbf_load_multiple_GR (SIM_CPU *, PCADDR, SI, SI, int);
-void frvbf_load_multiple_FRint (SIM_CPU *, PCADDR, SI, SI, int);
-void frvbf_load_multiple_CPR (SIM_CPU *, PCADDR, SI, SI, int);
-void frvbf_store_multiple_GR (SIM_CPU *, PCADDR, SI, SI, int);
-void frvbf_store_multiple_FRint (SIM_CPU *, PCADDR, SI, SI, int);
-void frvbf_store_multiple_CPR (SIM_CPU *, PCADDR, SI, SI, int);
+void frvbf_load_quad_GR (SIM_CPU *, PCADDR, SI, SI);
+void frvbf_load_quad_FRint (SIM_CPU *, PCADDR, SI, SI);
+void frvbf_load_quad_CPR (SIM_CPU *, PCADDR, SI, SI);
+void frvbf_store_quad_GR (SIM_CPU *, PCADDR, SI, SI);
+void frvbf_store_quad_FRint (SIM_CPU *, PCADDR, SI, SI);
+void frvbf_store_quad_CPR (SIM_CPU *, PCADDR, SI, SI);
 
 /* Memory and cache support.  */
 QI  frvbf_read_mem_QI  (SIM_CPU *, IADDR, SI);