/*> cp1.h <*/
/* MIPS Simulator FPU (CoProcessor 1) definitions.
- Copyright (C) 1997-2020 Free Software Foundation, Inc.
+ Copyright (C) 1997-2022 Free Software Foundation, Inc.
Derived from sim-main.h contributed by Cygnus Solutions,
modified substantially by Ed Satterthwaite of Broadcom Corporation
(SiByte).
#ifndef CP1_H
#define CP1_H
-/* See sim-main.h for allocation of registers FCR0 and FCR31 (FCSR)
+/* See sim-main.h for allocation of registers FCR0 and FCR31 (FCSR)
in CPU state (struct sim_cpu), and for FPU functions. */
#define fcsr_FCC_mask (0xFE800000)
#define fcsr_RM_mask (0x00000003)
#define fcsr_RM_shift (0)
+/* FCSR bits for IEEE754-2008 compliance. */
+#define fcsr_NAN2008_mask (0x00040000)
+#define fcsr_NAN2008_shift (18)
+#define fcsr_ABS2008_mask (0x00080000)
+#define fcsr_ABS2008_shift (19)
+
#define fenr_FS (0x00000004)
/* Macros to update and retrieve the FCSR condition-code bits. This