:model:::mipsV:mipsisaV:
:model:::mips32:mipsisa32:
:model:::mips32r2:mipsisa32r2:
+:model:::mips32r6:mipsisa32r6:
:model:::mips64:mipsisa64:
:model:::mips64r2:mipsisa64r2:
+:model:::mips64r6:mipsisa64r6:
// Vendor ISAs:
//
-// Helper:
+// Helpers:
+//
+// Check if given instruction is CTI, if so signal
+//
+:function:::void:signal_if_cti:instruction_word instr
+{
+ uint32_t maj = (instr & 0xfc000000) >> 26;
+ uint32_t special = instr & 0x3f;
+ if ((maj & 0x3e) == 0x06 /* Branch/Jump */
+ || ((maj & 0x38) == 0 && !((maj & 0x6) == 0))
+ || maj == 0x18
+ || (maj & 0x37) == 0x32
+ || (maj & 0x37) == 0x36
+ || ((maj == 0) && (special == 0x9))
+ /* DERET/ERET/WAIT */
+ || ((maj == 0x10) && (instr & 0x02000000)
+ && (special == 0x1f || special == 0x18 || special == 0x20)))
+ {
+ SignalException (ReservedInstruction, instr);
+ }
+}
+
//
// Simulate a 32 bit delayslot instruction
//
CIA = CIA + 4; /* NOTE not mips16 */
STATE |= simDELAYSLOT;
delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
+ signal_if_cti (SD_, delay_insn);
ENGINE_ISSUE_PREFIX_HOOK();
idecode_issue (CPU_, delay_insn, (CIA));
STATE &= ~simDELAYSLOT;
return target;
}
+//
+// Simulate a 32 bit forbidden slot instruction
+//
+
+:function:::address_word:forbiddenslot32:
+*mips32r6:
+*mips64r6:
+{
+ instruction_word delay_insn;
+ sim_events_slip (SD, 1);
+ DSPC = CIA;
+ CIA = CIA + 4;
+ STATE |= simFORBIDDENSLOT;
+ delay_insn = IMEM32 (CIA);
+ signal_if_cti (SD_, delay_insn);
+ ENGINE_ISSUE_PREFIX_HOOK ();
+ idecode_issue (CPU_, delay_insn, (CIA));
+ STATE &= ~simFORBIDDENSLOT;
+ return CIA + 4;
+}
+
:function:::address_word:nullify_next_insn32:
{
sim_events_slip (SD, 1);
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*vr4100:
*vr5000:
*r3900:
*mips64:
*mips64r2:
*micromips64:
+*mips64r6:
{
#if 0 /* XXX FIXME: enable this only after some additional testing. */
/* If in user mode and UX is not set, use 32-bit compatibility effective
Programmers Volume III, Revision 0.95, section 4.9. */
if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
== (ksu_user << status_KSU_shift))
- return (address_word)((signed32)base + (signed32)offset);
+ return (address_word)((int32_t)base + (int32_t)offset);
#endif
return base + offset;
}
*r3900:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
*micromips32:
*micromips64:
+*mips64r6:
{
#if WITH_TARGET_WORD_BITSIZE == 64
return value != (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
:function:::void:unpredictable:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
*micromips32:
*micromips64:
+*mips64r6:
{
unpredictable_action (CPU, CIA);
}
// Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo
// to check for restrictions (2) and (3) above.
//
-:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
+:function:::int:check_mf_cycles:hilo_history *history, int64_t time, const char *new
{
if (history->mf.timestamp + 3 > time)
{
*vr4100:
*vr5000:
{
- signed64 time = sim_events_time (SD);
+ int64_t time = sim_events_time (SD);
int ok = check_mf_cycles (SD_, history, time, "MT");
history->mt.timestamp = time;
history->mt.cia = CIA;
*mipsIV:
*mipsV:
{
- signed64 time = sim_events_time (SD);
+ int64_t time = sim_events_time (SD);
int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD)
|| check_mf_cycles (SD_, history, time, "MT"));
history->mt.timestamp = time;
:function:::int:check_mt_hilo:hilo_history *history
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*r3900:
*micromips32:
*micromips64:
{
- signed64 time = sim_events_time (SD);
+ int64_t time = sim_events_time (SD);
history->mt.timestamp = time;
history->mt.cia = CIA;
return 1;
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*micromips32:
*micromips64:
{
- signed64 time = sim_events_time (SD);
+ int64_t time = sim_events_time (SD);
int ok = 1;
if (peer != NULL
&& peer->mt.timestamp > history->op.timestamp
*vr4100:
*vr5000:
{
- signed64 time = sim_events_time (SD);
+ int64_t time = sim_events_time (SD);
int ok = (check_mf_cycles (SD_, hi, time, "OP")
&& check_mf_cycles (SD_, lo, time, "OP"));
hi->op.timestamp = time;
*mipsIV:
*mipsV:
{
- signed64 time = sim_events_time (SD);
+ int64_t time = sim_events_time (SD);
int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD)
|| (check_mf_cycles (SD_, hi, time, "OP")
&& check_mf_cycles (SD_, lo, time, "OP")));
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*r3900:
*micromips32:
*micromips64:
{
/* FIXME: could record the fact that a stall occured if we want */
- signed64 time = sim_events_time (SD);
+ int64_t time = sim_events_time (SD);
hi->op.timestamp = time;
lo->op.timestamp = time;
hi->op.cia = CIA;
*vr5000:
*r3900:
{
- signed64 time = sim_events_time (SD);
+ int64_t time = sim_events_time (SD);
int ok = (check_mf_cycles (SD_, hi, time, "OP")
&& check_mf_cycles (SD_, lo, time, "OP"));
hi->op.timestamp = time;
*mipsIV:
*mipsV:
{
- signed64 time = sim_events_time (SD);
+ int64_t time = sim_events_time (SD);
int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD)
|| (check_mf_cycles (SD_, hi, time, "OP")
&& check_mf_cycles (SD_, lo, time, "OP")));
:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
*micromips32:
*micromips64:
+*mips64r6:
{
- signed64 time = sim_events_time (SD);
+ int64_t time = sim_events_time (SD);
hi->op.timestamp = time;
lo->op.timestamp = time;
hi->op.cia = CIA;
*mips64r2:
*mips32:
*mips32r2:
+*mips32r6:
*micromips64:
*micromips32:
+*mips64r6:
{
#if 0 /* XXX FIXME: enable this only after some additional testing. */
if (UserMode && (SR & (status_UX|status_PX)) == 0)
TRACE_ALU_RESULT (GPR[rd]);
}
-:function:::void:do_addi:int rs, int rt, unsigned16 immediate
+:function:::void:do_addi:int rs, int rt, uint16_t immediate
{
if (NotWordValue (GPR[rs]))
Unpredictable ();
{
int s = 32 + shift;
TRACE_ALU_INPUT2 (GPR[rt], s);
- GPR[rd] = ((signed64) GPR[rt]) >> s;
+ GPR[rd] = ((int64_t) GPR[rt]) >> s;
TRACE_ALU_RESULT (GPR[rd]);
}
{
int s = 32 + shift;
TRACE_ALU_INPUT2 (GPR[rt], s);
- GPR[rd] = (unsigned64) GPR[rt] >> s;
+ GPR[rd] = (uint64_t) GPR[rt] >> s;
TRACE_ALU_RESULT (GPR[rd]);
}
:function:::void:do_clo:int rd, int rs
{
- unsigned32 temp = GPR[rs];
- unsigned32 i, mask;
+ uint32_t temp = GPR[rs];
+ uint32_t i, mask;
if (NotWordValue (GPR[rs]))
Unpredictable ();
TRACE_ALU_INPUT1 (GPR[rs]);
- for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
+ for (mask = ((uint32_t)1<<31), i = 0; i < 32; ++i)
{
if ((temp & mask) == 0)
break;
:function:::void:do_clz:int rd, int rs
{
- unsigned32 temp = GPR[rs];
- unsigned32 i, mask;
+ uint32_t temp = GPR[rs];
+ uint32_t i, mask;
if (NotWordValue (GPR[rs]))
Unpredictable ();
TRACE_ALU_INPUT1 (GPR[rs]);
- for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
+ for (mask = ((uint32_t)1<<31), i = 0; i < 32; ++i)
{
if ((temp & mask) != 0)
break;
:function:::void:do_dclo:int rd, int rs
{
- unsigned64 temp = GPR[rs];
- unsigned32 i;
- unsigned64 mask;
+ uint64_t temp = GPR[rs];
+ uint32_t i;
+ uint64_t mask;
TRACE_ALU_INPUT1 (GPR[rs]);
- for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
+ for (mask = ((uint64_t)1<<63), i = 0; i < 64; ++i)
{
if ((temp & mask) == 0)
break;
:function:::void:do_dclz:int rd, int rs
{
- unsigned64 temp = GPR[rs];
- unsigned32 i;
- unsigned64 mask;
+ uint64_t temp = GPR[rs];
+ uint32_t i;
+ uint64_t mask;
TRACE_ALU_INPUT1 (GPR[rs]);
- for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
+ for (mask = ((uint64_t)1<<63), i = 0; i < 64; ++i)
{
if ((temp & mask) != 0)
break;
}
else
{
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ uint64_t memval = 0;
+ uint64_t memval1 = 0;
+ uint64_t mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
unsigned int shift = 2;
unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
}
else
{
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
+ uint64_t memval = 0;
+ uint64_t memval1 = 0;
LoadMemory (&memval, &memval1, AccessLength_DOUBLEWORD, paddr, vaddr,
isDATA, isREAL);
GPR[rt] = memval;
:function:::void:do_madd:int rs, int rt
{
- signed64 temp;
+ int64_t temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
- + ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs])));
+ + ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs])));
LO = EXTEND32 (temp);
HI = EXTEND32 (VH4_8 (temp));
TRACE_ALU_RESULT2 (HI, LO);
:function:::void:do_dsp_madd:int ac, int rs, int rt
{
- signed64 temp;
+ int64_t temp;
if (ac == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
- + ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs])));
+ + ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs])));
DSPLO(ac) = EXTEND32 (temp);
DSPHI(ac) = EXTEND32 (VH4_8 (temp));
if (ac == 0)
:function:::void:do_maddu:int rs, int rt
{
- unsigned64 temp;
+ uint64_t temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
- + ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt])));
+ + ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt])));
ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
LO = EXTEND32 (temp);
HI = EXTEND32 (VH4_8 (temp));
:function:::void:do_dsp_maddu:int ac, int rs, int rt
{
- unsigned64 temp;
+ uint64_t temp;
if (ac == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
- + ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt])));
+ + ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt])));
if (ac == 0)
ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
DSPLO(ac) = EXTEND32 (temp);
:function:::void:do_msub:int rs, int rt
{
- signed64 temp;
+ int64_t temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
- - ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs])));
+ - ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs])));
LO = EXTEND32 (temp);
HI = EXTEND32 (VH4_8 (temp));
TRACE_ALU_RESULT2 (HI, LO);
:function:::void:do_dsp_msub:int ac, int rs, int rt
{
- signed64 temp;
+ int64_t temp;
if (ac == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
- - ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs])));
+ - ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs])));
DSPLO(ac) = EXTEND32 (temp);
DSPHI(ac) = EXTEND32 (VH4_8 (temp));
if (ac == 0)
:function:::void:do_msubu:int rs, int rt
{
- unsigned64 temp;
+ uint64_t temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
- - ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt])));
+ - ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt])));
LO = EXTEND32 (temp);
HI = EXTEND32 (VH4_8 (temp));
TRACE_ALU_RESULT2 (HI, LO);
:function:::void:do_dsp_msubu:int ac, int rs, int rt
{
- unsigned64 temp;
+ uint64_t temp;
if (ac == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
- - ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt])));
+ - ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt])));
DSPLO(ac) = EXTEND32 (temp);
DSPHI(ac) = EXTEND32 (VH4_8 (temp));
if (ac == 0)
:function:::void:do_mul:int rd, int rs, int rt
{
- signed64 prod;
+ int64_t prod;
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
- prod = (((signed64)(signed32) GPR[rs])
- * ((signed64)(signed32) GPR[rt]));
+ prod = (((int64_t)(int32_t) GPR[rs])
+ * ((int64_t)(int32_t) GPR[rt]));
GPR[rd] = EXTEND32 (VL4_8 (prod));
TRACE_ALU_RESULT (GPR[rd]);
}
:function:::void:do_dsp_mult:int ac, int rs, int rt
{
- signed64 prod;
+ int64_t prod;
if (ac == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
- prod = ((signed64)(signed32) GPR[rs])
- * ((signed64)(signed32) GPR[rt]);
+ prod = ((int64_t)(int32_t) GPR[rs])
+ * ((int64_t)(int32_t) GPR[rt]);
DSPLO(ac) = EXTEND32 (VL4_8 (prod));
DSPHI(ac) = EXTEND32 (VH4_8 (prod));
if (ac == 0)
:function:::void:do_dsp_multu:int ac, int rs, int rt
{
- unsigned64 prod;
+ uint64_t prod;
if (ac == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
- prod = ((unsigned64)(unsigned32) GPR[rs])
- * ((unsigned64)(unsigned32) GPR[rt]);
+ prod = ((uint64_t)(uint32_t) GPR[rs])
+ * ((uint64_t)(uint32_t) GPR[rt]);
DSPLO(ac) = EXTEND32 (VL4_8 (prod));
DSPHI(ac) = EXTEND32 (VH4_8 (prod));
if (ac == 0)
}
}
-:function:::void:do_sc:int rt, int offsetarg, int basereg, address_word instruction_0
+:function:::void:do_sc:int rt, int offsetarg, int basereg, address_word instruction_0, int store_ll_bit
{
- unsigned32 instruction = instruction_0;
+ uint32_t instruction = instruction_0;
address_word base = GPR[basereg];
address_word offset = EXTEND16 (offsetarg);
{
}
else
{
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ uint64_t memval = 0;
+ uint64_t memval1 = 0;
+ uint64_t mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
address_word reverseendian =
(ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
address_word bigendiancpu =
unsigned int byte;
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
byte = ((vaddr & mask) ^ bigendiancpu);
- memval = ((unsigned64) GPR[rt] << (8 * byte));
+ memval = ((uint64_t) GPR[rt] << (8 * byte));
if (LLBIT)
StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr,
isREAL);
- GPR[rt] = LLBIT;
+ if (store_ll_bit)
+ GPR[rt] = LLBIT;
}
}
}
-:function:::void:do_scd:int rt, int roffset, int rbase
+:function:::void:do_scd:int rt, int roffset, int rbase, int store_ll_bit
{
address_word base = GPR[rbase];
address_word offset = EXTEND16 (roffset);
}
else
{
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
+ uint64_t memval = 0;
+ uint64_t memval1 = 0;
memval = GPR[rt];
if (LLBIT)
StoreMemory (AccessLength_DOUBLEWORD, memval, memval1, paddr, vaddr,
isREAL);
- GPR[rt] = LLBIT;
+ if (store_ll_bit)
+ GPR[rt] = LLBIT;
}
}
}
:function:::void:do_alnv_ps:int fd, int fs, int ft, int rs, address_word instruction_0
{
- unsigned64 fsx;
- unsigned64 ftx;
- unsigned64 fdx;
+ uint64_t fsx;
+ uint64_t ftx;
+ uint64_t fdx;
check_fpu (SD_);
check_u64 (SD_, instruction_0);
fsx = ValueFPR (fs, fmt_ps);
*mipsV:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
}
else
{
- unsigned64 fdx;
+ uint64_t fdx;
fdx = PackPS (PSUpper (ValueFPR ((GETFCC (cc+1) == tf) ? fs : fd,
fmt_ps)),
PSLower (ValueFPR ((GETFCC (cc+0) == tf) ? fs : fd,
*mipsII:
*mips32:
*mips32r2:
+*mips32r6:
*micromips32:
{
check_fpu (SD_);
}
else
{
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ uint64_t memval = 0;
+ uint64_t memval1 = 0;
+ uint64_t mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
address_word reverseendian =
(ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
address_word bigendiancpu =
unsigned int byte;
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
byte = ((vaddr & mask) ^ bigendiancpu);
- memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
+ memval = (((uint64_t)COP_SW(1,fs)) << (8 * byte));
StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr,
isREAL);
}
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
-:function:::void:do_addiu:int rs, int rt, unsigned16 immediate
+:function:::void:do_addiu:int rs, int rt, uint16_t immediate
{
if (NotWordValue (GPR[rs]))
Unpredictable ();
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
}
+000100,5.RS,5.RT,16.OFFSET:R6:32::BEQ
+"beq r<RS>, r<RT>, <OFFSET>"
+*mips32r6:
+*mips64r6:
+{
+ address_word offset = EXTEND16 (OFFSET) << 2;
+ if (GPR[RS] == GPR[RT])
+ DELAY_SLOT (NIA + offset);
+ else
+ FORBIDDEN_SLOT ();
+}
010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
"beql r<RS>, r<RT>, <OFFSET>"
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
}
}
-
+000001,00000,10001,16.OFFSET:REGIMM:32::BAL
+"bal <OFFSET>"
+*mips32r6:
+*mips64r6:
+{
+ address_word offset = EXTEND16 (OFFSET) << 2;
+ RA = (CIA + 8);
+ DELAY_SLOT (NIA + offset);
+}
000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
"bgezall r<RS>, <OFFSET>"
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
+000001,00000,10000,16.OFFSET:REGIMM:32::NAL
+"nal <OFFSET>"
+*mips32r6:
+*mips64r6:
+{
+ address_word offset = EXTEND16 (OFFSET) << 2;
+ RA = (CIA + 8);
+ FORBIDDEN_SLOT ();
+}
+
+
+
000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
"bltzall r<RS>, <OFFSET>"
*mipsII:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
{
-:function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
+:function:::void:do_daddiu:int rs, int rt, uint16_t immediate
{
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
GPR[rt] = GPR[rs] + EXTEND16 (immediate);
*mipsV:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
{
*mipsV:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
{
if (RT != RD)
Unpredictable ();
check_u64 (SD_, instruction_0);
+ if (RT != RD)
+ Unpredictable ();
do_dclo (SD_, RD, RS);
}
if (RT != RD)
Unpredictable ();
check_u64 (SD_, instruction_0);
+ if (RT != RD)
+ Unpredictable ();
do_dclz (SD_, RD, RS);
}
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
- signed64 n = GPR[rs];
- signed64 d = GPR[rt];
- signed64 hi;
- signed64 lo;
+ int64_t n = GPR[rs];
+ int64_t d = GPR[rt];
+ int64_t hi;
+ int64_t lo;
if (d == 0)
{
lo = SIGNED64 (0x8000000000000000);
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
- unsigned64 n = GPR[rs];
- unsigned64 d = GPR[rt];
- unsigned64 hi;
- unsigned64 lo;
+ uint64_t n = GPR[rs];
+ uint64_t d = GPR[rt];
+ uint64_t hi;
+ uint64_t lo;
if (d == 0)
{
lo = SIGNED64 (0x8000000000000000);
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
- signed32 n = GPR[rs];
- signed32 d = GPR[rt];
+ int32_t n = GPR[rs];
+ int32_t d = GPR[rt];
if (d == 0)
{
LO = EXTEND32 (0x80000000);
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
- unsigned32 n = GPR[rs];
- unsigned32 d = GPR[rt];
+ uint32_t n = GPR[rs];
+ uint32_t d = GPR[rt];
if (d == 0)
{
LO = EXTEND32 (0x80000000);
:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
{
- unsigned64 lo;
- unsigned64 hi;
- unsigned64 m00;
- unsigned64 m01;
- unsigned64 m10;
- unsigned64 m11;
- unsigned64 mid;
+ uint64_t lo;
+ uint64_t hi;
+ uint64_t m00;
+ uint64_t m01;
+ uint64_t m10;
+ uint64_t m11;
+ uint64_t mid;
int sign;
- unsigned64 op1 = GPR[rs];
- unsigned64 op2 = GPR[rt];
+ uint64_t op1 = GPR[rs];
+ uint64_t op2 = GPR[rt];
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
/* make signed multiply unsigned */
sign = 0;
if (signed_p)
{
- if ((signed64) op1 < 0)
+ if ((int64_t) op1 < 0)
{
op1 = - op1;
++sign;
}
- if ((signed64) op2 < 0)
+ if ((int64_t) op2 < 0)
{
op2 = - op2;
++sign;
}
}
/* multiply out the 4 sub products */
- m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
- m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
- m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
- m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
+ m00 = ((uint64_t) VL4_8 (op1) * (uint64_t) VL4_8 (op2));
+ m10 = ((uint64_t) VH4_8 (op1) * (uint64_t) VL4_8 (op2));
+ m01 = ((uint64_t) VL4_8 (op1) * (uint64_t) VH4_8 (op2));
+ m11 = ((uint64_t) VH4_8 (op1) * (uint64_t) VH4_8 (op2));
/* add the products */
- mid = ((unsigned64) VH4_8 (m00)
- + (unsigned64) VL4_8 (m10)
- + (unsigned64) VL4_8 (m01));
+ mid = ((uint64_t) VH4_8 (m00)
+ + (uint64_t) VL4_8 (m10)
+ + (uint64_t) VL4_8 (m01));
lo = U8_4 (mid, m00);
hi = (m11
- + (unsigned64) VH4_8 (mid)
- + (unsigned64) VH4_8 (m01)
- + (unsigned64) VH4_8 (m10));
+ + (uint64_t) VH4_8 (mid)
+ + (uint64_t) VH4_8 (m01)
+ + (uint64_t) VH4_8 (m10));
/* fix the sign */
if (sign & 1)
{
}
-:function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
+:function:::uint64_t:do_dror:uint64_t x,uint64_t y
{
- unsigned64 result;
+ uint64_t result;
y &= 63;
TRACE_ALU_INPUT2 (x, y);
000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
"dror r<RD>, r<RT>, <SHIFT>"
*mips64r2:
+*mips64r6:
*vr5400:
*vr5500:
{
000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
"dror32 r<RD>, r<RT>, <SHIFT>"
*mips64r2:
+*mips64r6:
*vr5400:
*vr5500:
{
000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
"drorv r<RD>, r<RT>, r<RS>"
*mips64r2:
+*mips64r6:
*vr5400:
*vr5500:
{
*mipsV:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
{
*mipsV:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
{
*mipsV:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
{
:function:::void:do_dsra:int rt, int rd, int shift
{
TRACE_ALU_INPUT2 (GPR[rt], shift);
- GPR[rd] = ((signed64) GPR[rt]) >> shift;
+ GPR[rd] = ((int64_t) GPR[rt]) >> shift;
TRACE_ALU_RESULT (GPR[rd]);
}
*mipsV:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
{
*mipsV:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
{
{
int s = MASKED64 (GPR[rs], 5, 0);
TRACE_ALU_INPUT2 (GPR[rt], s);
- GPR[rd] = ((signed64) GPR[rt]) >> s;
+ GPR[rd] = ((int64_t) GPR[rt]) >> s;
TRACE_ALU_RESULT (GPR[rd]);
}
*mipsV:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
{
:function:::void:do_dsrl:int rt, int rd, int shift
{
TRACE_ALU_INPUT2 (GPR[rt], shift);
- GPR[rd] = (unsigned64) GPR[rt] >> shift;
+ GPR[rd] = (uint64_t) GPR[rt] >> shift;
TRACE_ALU_RESULT (GPR[rd]);
}
*mipsV:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
{
*mipsV:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
{
{
int s = MASKED64 (GPR[rs], 5, 0);
TRACE_ALU_INPUT2 (GPR[rt], s);
- GPR[rd] = (unsigned64) GPR[rt] >> s;
+ GPR[rd] = (uint64_t) GPR[rt] >> s;
TRACE_ALU_RESULT (GPR[rd]);
}
*mipsV:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
{
*mipsV:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
{
*mipsV:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
{
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
"jalr.hb r<RS>":RD == 31
"jalr.hb r<RD>, r<RS>"
*mips32r2:
+*mips32r6:
*mips64r2:
+*mips64r6:
{
address_word temp = GPR[RS];
GPR[RD] = CIA + 8;
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
000000,5.RS,0000000000,10000,001000:SPECIAL:32::JR_HB
"jr.hb r<RS>"
*mips32r2:
+*mips32r6:
*mips64r2:
+*mips64r6:
{
DELAY_SLOT (GPR[RS]);
}
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
unsigned int byte;
address_word paddr;
- unsigned64 memval;
+ uint64_t memval;
address_word vaddr;
paddr = vaddr = loadstore_ea (SD_, base, offset);
unsigned int byte;
unsigned int word;
address_word paddr;
- unsigned64 memval;
+ uint64_t memval;
address_word vaddr;
int nr_lhs_bits;
int nr_rhs_bits;
/* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
/* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
- (long) ((unsigned64) vaddr >> 32), (long) vaddr,
- (long) ((unsigned64) paddr >> 32), (long) paddr,
+ (long) ((uint64_t) vaddr >> 32), (long) vaddr,
+ (long) ((uint64_t) paddr >> 32), (long) paddr,
word, byte, nr_lhs_bits, nr_rhs_bits); */
LoadMemory (&memval, NULL, byte, paddr, vaddr, isDATA, isREAL);
rt = (rt & ~lhs_mask) | (temp & lhs_mask);
/* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
- (long) ((unsigned64) memval >> 32), (long) memval,
- (long) ((unsigned64) temp >> 32), (long) temp,
- (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
+ (long) ((uint64_t) memval >> 32), (long) memval,
+ (long) ((uint64_t) temp >> 32), (long) temp,
+ (long) ((uint64_t) lhs_mask >> 32), (long) lhs_mask,
(long) (rt >> 32), (long) rt); */
return rt;
}
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
unsigned int byte;
address_word paddr;
- unsigned64 memval;
+ uint64_t memval;
address_word vaddr;
paddr = vaddr = loadstore_ea (SD_, base, offset);
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
{
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
{
:function:::void:do_mult:int rs, int rt, int rd
{
- signed64 prod;
+ int64_t prod;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
- prod = (((signed64)(signed32) GPR[rs])
- * ((signed64)(signed32) GPR[rt]));
+ prod = (((int64_t)(int32_t) GPR[rs])
+ * ((int64_t)(int32_t) GPR[rt]));
LO = EXTEND32 (VL4_8 (prod));
HI = EXTEND32 (VH4_8 (prod));
ACX = 0; /* SmartMIPS */
:function:::void:do_multu:int rs, int rt, int rd
{
- unsigned64 prod;
+ uint64_t prod;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
- prod = (((unsigned64)(unsigned32) GPR[rs])
- * ((unsigned64)(unsigned32) GPR[rt]));
+ prod = (((uint64_t)(uint32_t) GPR[rs])
+ * ((uint64_t)(uint32_t) GPR[rt]));
LO = EXTEND32 (VL4_8 (prod));
HI = EXTEND32 (VH4_8 (prod));
if (rd != 0)
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
}
-:function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
+:function:::uint64_t:do_ror:uint32_t x,uint32_t y
{
- unsigned64 result;
+ uint64_t result;
y &= 31;
TRACE_ALU_INPUT2 (x, y);
000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
"ror r<RD>, r<RT>, <SHIFT>"
*mips32r2:
+*mips32r6:
*mips64r2:
+*mips64r6:
*smartmips:
*vr5400:
*vr5500:
000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
"rorv r<RD>, r<RT>, r<RS>"
*mips32r2:
+*mips32r6:
*mips64r2:
+*mips64r6:
*smartmips:
*vr5400:
*vr5500:
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
unsigned int byte;
address_word paddr;
- unsigned64 memval;
+ uint64_t memval;
address_word vaddr;
paddr = vaddr = loadstore_ea (SD_, base, offset);
unsigned int byte;
unsigned int word;
address_word paddr;
- unsigned64 memval;
+ uint64_t memval;
address_word vaddr;
int nr_lhs_bits;
int nr_rhs_bits;
nr_rhs_bits = 8 * access - 8 * byte;
/* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
/* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
- (long) ((unsigned64) vaddr >> 32), (long) vaddr,
- (long) ((unsigned64) paddr >> 32), (long) paddr,
+ (long) ((uint64_t) vaddr >> 32), (long) vaddr,
+ (long) ((uint64_t) paddr >> 32), (long) paddr,
word, byte, nr_lhs_bits, nr_rhs_bits); */
if (word == 0)
memval = (rt << nr_lhs_bits);
}
/* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
- (long) ((unsigned64) rt >> 32), (long) rt,
- (long) ((unsigned64) memval >> 32), (long) memval); */
+ (long) ((uint64_t) rt >> 32), (long) rt,
+ (long) ((uint64_t) memval >> 32), (long) memval); */
StoreMemory (byte, memval, 0, paddr, vaddr, isREAL);
}
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
unsigned int byte;
address_word paddr;
- unsigned64 memval;
+ uint64_t memval;
address_word vaddr;
paddr = vaddr = loadstore_ea (SD_, base, offset);
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*vr4100:
*vr5000:
{
- do_sc (SD_, RT, OFFSET, BASE, instruction_0);
+ do_sc (SD_, RT, OFFSET, BASE, instruction_0, 1);
}
*vr5000:
{
check_u64 (SD_, instruction_0);
- do_scd (SD_, RT, OFFSET, BASE);
+ do_scd (SD_, RT, OFFSET, BASE, 1);
}
*mipsV:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
{
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
:function:::void:do_sll:int rt, int rd, int shift
{
- unsigned32 temp = (GPR[rt] << shift);
+ uint32_t temp = (GPR[rt] << shift);
TRACE_ALU_INPUT2 (GPR[rt], shift);
GPR[rd] = EXTEND32 (temp);
TRACE_ALU_RESULT (GPR[rd]);
000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
"nop":RD == 0 && RT == 0 && SHIFT == 0
"ssnop":RD == 0 && RT == 0 && SHIFT == 1
+"ehb":RD == 0 && RT == 0 && SHIFT == 3
"sll r<RD>, r<RT>, <SHIFT>"
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
{
- /* Skip shift for NOP and SSNOP, so that there won't be lots of
- extraneous trace output. */
- if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
- do_sll (SD_, RT, RD, SHIFT);
+ do_sll (SD_, RT, RD, SHIFT);
}
:function:::void:do_sllv:int rs, int rt, int rd
{
int s = MASKED (GPR[rs], 4, 0);
- unsigned32 temp = (GPR[rt] << s);
+ uint32_t temp = (GPR[rt] << s);
TRACE_ALU_INPUT2 (GPR[rt], s);
GPR[rd] = EXTEND32 (temp);
TRACE_ALU_RESULT (GPR[rd]);
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
}
-:function:::void:do_slti:int rs, int rt, unsigned16 immediate
+:function:::void:do_slti:int rs, int rt, uint16_t immediate
{
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
}
-:function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
+:function:::void:do_sltiu:int rs, int rt, uint16_t immediate
{
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
:function:::void:do_sra:int rt, int rd, int shift
{
- signed32 temp = (signed32) GPR[rt] >> shift;
+ int32_t temp = (int32_t) GPR[rt] >> shift;
if (NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rt], shift);
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
:function:::void:do_srav:int rs, int rt, int rd
{
int s = MASKED (GPR[rs], 4, 0);
- signed32 temp = (signed32) GPR[rt] >> s;
+ int32_t temp = (int32_t) GPR[rt] >> s;
if (NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rt], s);
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
:function:::void:do_srl:int rt, int rd, int shift
{
- unsigned32 temp = (unsigned32) GPR[rt] >> shift;
+ uint32_t temp = (uint32_t) GPR[rt] >> shift;
if (NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rt], shift);
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
:function:::void:do_srlv:int rs, int rt, int rd
{
int s = MASKED (GPR[rs], 4, 0);
- unsigned32 temp = (unsigned32) GPR[rt] >> s;
+ uint32_t temp = (uint32_t) GPR[rt] >> s;
if (NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rt], s);
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*r3900:
*vr5000:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
{
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
{
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
{
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
{
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
{
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
{
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
}
-:function:::void:do_xori:int rs, int rt, unsigned16 immediate
+:function:::void:do_xori:int rs, int rt, uint16_t immediate
{
TRACE_ALU_INPUT2 (GPR[rs], immediate);
GPR[rt] = GPR[rs] ^ immediate;
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mips32:
+*mips32r6:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
{
if (! COP_Usable (1))
SignalExceptionCoProcessorUnusable (1);
+
+ FCSR &= ~(fcsr_NAN2008_mask | fcsr_ABS2008_mask);
+ sim_fpu_quiet_nan_inverted = true;
}
+// Helper:
+//
+// Check that the FPU is currently usable, and signal a CoProcessorUnusable
+// exception if not.
+//
+
+:function:::void:check_fpu:
+*mips32r6:
+*mips64r6:
+{
+ if (! COP_Usable (1))
+ SignalExceptionCoProcessorUnusable (1);
+
+ FCSR |= (fcsr_NAN2008_mask | fcsr_ABS2008_mask);
+ sim_fpu_quiet_nan_inverted = 0;
+ sim_fpu_set_mode (sim_fpu_ieee754_2008);
+}
// Helper:
//
// unsigned_word, which is limited to the size of the machine's registers.
//
-:function:::unsigned64:do_load_double:address_word base, address_word offset
+:function:::uint64_t:do_load_double:address_word base, address_word offset
*mipsII:
*mips32:
*mips32r2:
+*mips32r6:
*micromips32:
{
int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
address_word vaddr;
address_word paddr;
- unsigned64 memval;
- unsigned64 v;
+ uint64_t memval;
+ uint64_t v;
paddr = vaddr = loadstore_ea (SD_, base, offset);
if ((vaddr & AccessLength_DOUBLEWORD) != 0)
sim_core_unaligned_signal);
}
LoadMemory (&memval, NULL, AccessLength_WORD, paddr, vaddr, isDATA, isREAL);
- v = (unsigned64)memval;
+ v = (uint64_t)memval;
LoadMemory (&memval, NULL, AccessLength_WORD, paddr + 4, vaddr + 4, isDATA,
isREAL);
return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
// unsigned_word, which is limited to the size of the machine's registers.
//
-:function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
+:function:::void:do_store_double:address_word base, address_word offset, uint64_t v
*mipsII:
*mips32:
*mips32r2:
*micromips32:
+ *mips32r6:
{
int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
address_word vaddr;
address_word paddr;
- unsigned64 memval;
+ uint64_t memval;
paddr = vaddr = loadstore_ea (SD_, base, offset);
if ((vaddr & AccessLength_DOUBLEWORD) != 0)
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
{
do_cfc1 (SD_, RT, FS);
}
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
{
do_ctc1 (SD_, RT, FS);
}
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
"dmfc1 r<RT>, f<FS>"
*mipsIII:
{
- unsigned64 v;
+ uint64_t v;
check_fpu (SD_);
check_u64 (SD_, instruction_0);
if (SizeFGR () == 64)
*mipsV:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
"dmtc1 r<RT>, f<FS>"
*mipsIII:
{
- unsigned64 v;
+ uint64_t v;
check_fpu (SD_);
check_u64 (SD_, instruction_0);
if (SizeFGR () == 64)
*mipsV:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsII:
*mips32:
*mips32r2:
+*mips32r6:
{
check_fpu (SD_);
COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
*mipsV:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsII:
*mipsIII:
{
- unsigned64 v;
+ uint64_t v;
check_fpu (SD_);
v = EXTEND32 (FGR[FS]);
PENDING_FILL (RT, v);
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr5000:
{
do_recip_fmt (SD_, FMT, FD, FS);
*mipsIV:
*mipsV:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr5000:
{
do_rsqrt_fmt (SD_, FMT, FD, FS);
*mipsII:
*mips32:
*mips32r2:
+*mips32r6:
{
do_sdc1 (SD_, FT, OFFSET, BASE);
}
*mipsV:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:32,f::SDXC1
"sdxc1 f<FS>, r<INDEX>(r<BASE>)"
-*mips32r2
+*mips32r2:
{
check_fpu (SD_);
do_store_double (SD_, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
+:function:::void:do_cache:int op, int rbase, int roffset, address_word instruction_0
+{
+ address_word base = GPR[rbase];
+ address_word offset = EXTEND16 (roffset);
+ {
+ address_word vaddr = loadstore_ea (SD_, base, offset);
+ address_word paddr = vaddr;
+ CacheOp(op, vaddr, paddr, instruction_0);
+ }
+}
101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
"cache <OP>, <OFFSET>(r<BASE>)"
*vr5000:
*r3900:
{
- address_word base = GPR[BASE];
- address_word offset = EXTEND16 (OFFSET);
- {
- address_word vaddr = loadstore_ea (SD_, base, offset);
- address_word paddr = vaddr;
- CacheOp(OP, vaddr, paddr, instruction_0);
- }
+ do_cache (SD_, OP, BASE, OFFSET, instruction_0);
}
*mipsV:
*mips64:
*mips64r2:
+*mips64r6:
{
check_u64 (SD_, instruction_0);
DecodeCoproc (instruction_0, 0, cp0_dmfc0, RT, RD, SEL);
*mipsV:
*mips64:
*mips64r2:
+*mips64r6:
{
check_u64 (SD_, instruction_0);
DecodeCoproc (instruction_0, 0, cp0_dmtc0, RT, RD, SEL);
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
{
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*r3900:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*r3900:
{
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
*mipsV:
*mips32:
*mips32r2:
+*mips32r6:
*mips64:
*mips64r2:
+*mips64r6:
*vr4100:
*vr5000:
:include:::mips3264r2.igen
+:include:::mips3264r6.igen
:include:::m16.igen
:include:::m16e.igen
:include:::mdmx.igen