Smooth some of ALU tracing's rough edges.

[binutils-gdb.git] / sim / v850 / ChangeLog

diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog
index 2785dc984f24440439dd9dfb03465493f9f00bfe..1b1b2b5e909f318a6490fbeafe8ea221f857572a 100644 (file)
--- a/sim/v850/ChangeLog
+++ b/sim/v850/ChangeLog
@@ -1,3 +1,75 @@
+Tue Sep 16 22:14:01 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+       * simops.c (trace_output): Add result argument.
+       (trace_result): New function.  Simpler version of trace_output,
+       assumes trace needed.
+       (trace_output): Call trace_result.
+       (trace_output): For IMM_REG_REG, trace correct register.
+       (trace_input): Add case for 16bit immediates.
+       (OP_600, OP_640, OP_680, OP_6C0, OP_6A0): Use.
+
+       * sim-main.h (TRACE_ALU_INPUT, TRACE_ALU_RESULT): Define.
+       (trace_values, trace_name, trace_pc, trace_num_values): Make
+       global.
+       (GR, SR): Define.
+       
+       v850.insn (movea, stsr): Use.
+start-sanitize-v850e
+       (sxb, sxh, zxb, zxh): Ditto.
+end-sanitize-v850e
+       
+Tue Sep 16 21:14:01 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+       * simops.c: Move "movea" from here.
+       * v850.igen: To here.
+
+       * v850.igen (simm16): Define, sign extend imm16.
+       (uimm16): Define, no sign extension.
+       (addi, andi, movea, movhi, mulhi, ori, satsubi, xori): Use.
+       
+start-sanitize-v850e
+       * simops.c: Move "sxh", "switch", "sxb", "callt", "dispose",
+       "mov32" from here.
+       * v850.igen: To here.
+       (switch): Fix off by two error in NIA calc.
+       
+end-sanitize-v850e
+Tue Sep 16 15:14:01 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+       * simops.c (trace_pc, trace_name, trace_values, trace_num_values):
+       New static globals.
+       (trace_input): Just save pc, name and values for trace_output.
+       (trace_output): Write trace values to a buffer.  Use
+       trace_one_insn to print trace info and buffer.
+       (SIZE_OPERANDS, SIZE_LOCATION): Delete.
+       
+Tue Sep 16 09:02:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+       * sim-main.h (struct _sim_cpu): Add psw_mask so that reserved bits
+       can be masked out.
+
+       * simops.c (OP_2007E0, OP_4007E0): Move "ldsr", "stsr"
+       instructions from here.
+       * v850.igen (ldsr, stsr): To here.  Mask out reserved bits when
+       setting PSW.
+       
+       * interp.c (sim_open): Set psw_mask if machine known.
+
+Tue Sep 16 10:20:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+start-sanitize-v850e
+       * v850-dc: Add rule to diferentiate between breakpoint and divh.
+       * v850.igen (break): New instruction, breakpoint simulator.
+
+end-sanitize-v850e
+       * v850.igen (breakpoint): Enable.  Change to a 32bit instruction.
+
+start-sanitize-v850e
+Mon Sep 15 18:44:05 1997  Jim Wilson  <wilson@cygnus.com>
+
+       * simops.c (Multiply64): Don't store into register zero.
+
+start-sanitize-v850e
 Tue Sep 16 09:02:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 
        * Makefile.in (semantics.o): Add dependency.