-#include <signal.h>
-#include "sysdep.h"
-#include "bfd.h"
-#include "remote-sim.h"
-#include "callback.h"
-
+#include "sim-main.h"
+#include "sim-options.h"
#include "v850_sim.h"
+#include "sim-assert.h"
+#include "itable.h"
-#ifndef INLINE
-#ifdef __GNUC__
-#define INLINE inline
-#else
-#define INLINE
-#endif
-#endif
+#include <stdlib.h>
+#include <string.h>
-#define MEM_SIZE 18 /* V850 memory size is 18 bits XXX */
+#include "bfd.h"
-host_callback *v850_callback;
-int v850_debug;
+static const char * get_insn_name (sim_cpu *, int);
+/* For compatibility. */
+SIM_DESC simulator;
-uint32 OP[4];
+/* V850 interrupt model. */
-static struct hash_entry *lookup_hash PARAMS ((uint32 ins));
-static long hash PARAMS ((long));
-static void do_format_1_2 PARAMS ((uint32));
-static void do_format_3 PARAMS ((uint32));
-static void do_format_4 PARAMS ((uint32));
-static void do_format_5 PARAMS ((uint32));
-static void do_format_6 PARAMS ((uint32));
-static void do_format_7 PARAMS ((uint32));
-static void do_format_8 PARAMS ((uint32));
-static void do_format_9_10 PARAMS ((uint32));
-static void init_system PARAMS ((void));
-
-#define MAX_HASH 63
-struct hash_entry
+enum interrupt_type
{
- struct hash_entry *next;
- long opcode;
- long mask;
- struct simops *ops;
+ int_reset,
+ int_nmi,
+ int_intov1,
+ int_intp10,
+ int_intp11,
+ int_intp12,
+ int_intp13,
+ int_intcm4,
+ num_int_types
};
-struct hash_entry hash_table[MAX_HASH+1];
-
-
-static INLINE long
-hash(insn)
- long insn;
-{
- if ((insn & 0x0600) == 0
- || (insn & 0x0700) == 0x0200
- || (insn & 0x0700) == 0x0600
- || (insn & 0x0780) == 0x0700)
- return (insn & 0x07e0) >> 5;
- if ((insn & 0x0700) == 0x0300
- || (insn & 0x0700) == 0x0400
- || (insn & 0x0700) == 0x0500)
- return (insn & 0x0780) >> 7;
- if ((insn & 0x07c0) == 0x0780)
- return (insn & 0x07c0) >> 6;
- return (insn & 0x07e0) >> 5;
-}
+const char *interrupt_names[] =
+{
+ "reset",
+ "nmi",
+ "intov1",
+ "intp10",
+ "intp11",
+ "intp12",
+ "intp13",
+ "intcm4",
+ NULL
+};
-static struct hash_entry *
-lookup_hash (ins)
- uint32 ins;
+static void
+do_interrupt (SIM_DESC sd, void *data)
{
- struct hash_entry *h;
+ const char **interrupt_name = (const char**)data;
+ enum interrupt_type inttype;
+ inttype = (interrupt_name - STATE_WATCHPOINTS (sd)->interrupt_names);
- h = &hash_table[hash(ins)];
+ /* For a hardware reset, drop everything and jump to the start
+ address */
+ if (inttype == int_reset)
+ {
+ PC = 0;
+ PSW = 0x20;
+ ECR = 0;
+ sim_engine_restart (sd, NULL, NULL, NULL_CIA);
+ }
- while ((ins & h->mask) != h->opcode)
+ /* Deliver an NMI when allowed */
+ if (inttype == int_nmi)
{
- if (h->next == NULL)
+ if (PSW & PSW_NP)
+ {
+ /* We're already working on an NMI, so this one must wait
+ around until the previous one is done. The processor
+ ignores subsequent NMIs, so we don't need to count them.
+ Just keep re-scheduling a single NMI until it manages to
+ be delivered */
+ if (STATE_CPU (sd, 0)->pending_nmi != NULL)
+ sim_events_deschedule (sd, STATE_CPU (sd, 0)->pending_nmi);
+ STATE_CPU (sd, 0)->pending_nmi =
+ sim_events_schedule (sd, 1, do_interrupt, data);
+ return;
+ }
+ else
{
- (*v850_callback->printf_filtered) (v850_callback, "ERROR looking up hash for %x\n", ins);
- exit(1);
+ /* NMI can be delivered. Do not deschedule pending_nmi as
+ that, if still in the event queue, is a second NMI that
+ needs to be delivered later. */
+ FEPC = PC;
+ FEPSW = PSW;
+ /* Set the FECC part of the ECR. */
+ ECR &= 0x0000ffff;
+ ECR |= 0x10;
+ PSW |= PSW_NP;
+ PSW &= ~PSW_EP;
+ PSW |= PSW_ID;
+ PC = 0x10;
+ sim_engine_restart (sd, NULL, NULL, NULL_CIA);
}
- h = h->next;
}
- return (h);
-}
-
-uint8
-get_byte (x)
- uint8 *x;
-{
- return *x;
-}
-
-uint16
-get_half (x)
- uint8 *x;
-{
- uint8 *a = x;
- return (a[1] << 8) + (a[0]);
-}
-uint32
-get_word (x)
- uint8 *x;
-{
- uint8 *a = x;
- return (a[3]<<24) + (a[2]<<16) + (a[1]<<8) + (a[0]);
-}
-
-void
-put_byte (addr, data)
- uint8 *addr;
- uint8 data;
-{
- uint8 *a = addr;
- a[0] = data;
+ /* deliver maskable interrupt when allowed */
+ if (inttype > int_nmi && inttype < num_int_types)
+ {
+ if ((PSW & PSW_NP) || (PSW & PSW_ID))
+ {
+ /* Can't deliver this interrupt, reschedule it for later */
+ sim_events_schedule (sd, 1, do_interrupt, data);
+ return;
+ }
+ else
+ {
+ /* save context */
+ EIPC = PC;
+ EIPSW = PSW;
+ /* Disable further interrupts. */
+ PSW |= PSW_ID;
+ /* Indicate that we're doing interrupt not exception processing. */
+ PSW &= ~PSW_EP;
+ /* Clear the EICC part of the ECR, will set below. */
+ ECR &= 0xffff0000;
+ switch (inttype)
+ {
+ case int_intov1:
+ PC = 0x80;
+ ECR |= 0x80;
+ break;
+ case int_intp10:
+ PC = 0x90;
+ ECR |= 0x90;
+ break;
+ case int_intp11:
+ PC = 0xa0;
+ ECR |= 0xa0;
+ break;
+ case int_intp12:
+ PC = 0xb0;
+ ECR |= 0xb0;
+ break;
+ case int_intp13:
+ PC = 0xc0;
+ ECR |= 0xc0;
+ break;
+ case int_intcm4:
+ PC = 0xd0;
+ ECR |= 0xd0;
+ break;
+ default:
+ /* Should never be possible. */
+ sim_engine_abort (sd, NULL, NULL_CIA,
+ "do_interrupt - internal error - bad switch");
+ break;
+ }
+ }
+ sim_engine_restart (sd, NULL, NULL, NULL_CIA);
+ }
+
+ /* some other interrupt? */
+ sim_engine_abort (sd, NULL, NULL_CIA,
+ "do_interrupt - internal error - interrupt %d unknown",
+ inttype);
}
-void
-put_half (addr, data)
- uint8 *addr;
- uint16 data;
-{
- uint8 *a = addr;
- a[0] = data & 0xff;
- a[1] = (data >> 8) & 0xff;
-}
+/* Return name of an insn, used by insn profiling. */
-void
-put_word (addr, data)
- uint8 *addr;
- uint32 data;
+static const char *
+get_insn_name (sim_cpu *cpu, int i)
{
- uint8 *a = addr;
- a[0] = data & 0xff;
- a[1] = (data >> 8) & 0xff;
- a[2] = (data >> 16) & 0xff;
- a[3] = (data >> 24) & 0xff;
+ return itable[i].name;
}
-static void
-do_format_1_2 (insn)
- uint32 insn;
-{
- struct hash_entry *h;
+/* These default values correspond to expected usage for the chip. */
- h = lookup_hash (insn);
- OP[0] = insn & 0x1f;
- OP[1] = (insn >> 11) & 0x1f;
- (h->ops->func) ();
-}
+uint32 OP[4];
-static void
-do_format_3 (insn)
- uint32 insn;
+static sim_cia
+v850_pc_get (sim_cpu *cpu)
{
- struct hash_entry *h;
-
- h = lookup_hash (insn);
- OP[0] = (((insn & 0x70) >> 4) | ((insn & 0xf800) >> 8)) << 1;
- (h->ops->func) ();
+ return PC;
}
static void
-do_format_4 (insn)
- uint32 insn;
+v850_pc_set (sim_cpu *cpu, sim_cia pc)
{
- struct hash_entry *h;
-
- h = lookup_hash (insn);
- OP[0] = (insn >> 11) & 0x1f;
- OP[1] = (insn & 0x7f);
- (h->ops->func) ();
+ PC = pc;
}
-static void
-do_format_5 (insn)
- uint32 insn;
-{
- struct hash_entry *h;
-
- h = lookup_hash (insn);
- OP[0] = (((insn & 0x3f) << 15) | ((insn >> 17) & 0x7fff)) << 1;
- OP[1] = (insn >> 11) & 0x1f;
- (h->ops->func) ();
-}
+static int v850_reg_fetch (SIM_CPU *, int, unsigned char *, int);
+static int v850_reg_store (SIM_CPU *, int, unsigned char *, int);
-static void
-do_format_6 (insn)
- uint32 insn;
+SIM_DESC
+sim_open (SIM_OPEN_KIND kind,
+ host_callback * cb,
+ struct bfd * abfd,
+ char * const * argv)
{
- struct hash_entry *h;
-
- h = lookup_hash (insn);
- OP[0] = (insn >> 16) & 0xffff;
- OP[1] = insn & 0x1f;
- OP[2] = (insn >> 11) & 0x1f;
- (h->ops->func) ();
-}
+ int i;
+ SIM_DESC sd = sim_state_alloc (kind, cb);
+ int mach;
-static void
-do_format_7 (insn)
- uint32 insn;
-{
- struct hash_entry *h;
+ SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
- h = lookup_hash (insn);
- OP[0] = insn & 0x1f;
- OP[1] = (insn >> 11) & 0x1f;
- OP[2] = (insn >> 16) & 0xffff;
- (h->ops->func) ();
-}
+ /* The cpu data is kept in a separately allocated chunk of memory. */
+ if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
+ return 0;
-static void
-do_format_8 (insn)
- uint32 insn;
-{
- struct hash_entry *h;
+ /* for compatibility */
+ simulator = sd;
- h = lookup_hash (insn);
- OP[0] = insn & 0x1f;
- OP[1] = (insn >> 11) & 0x7;
- OP[2] = (insn >> 16) & 0xffff;
- (h->ops->func) ();
-}
+ /* FIXME: should be better way of setting up interrupts */
+ STATE_WATCHPOINTS (sd)->interrupt_handler = do_interrupt;
+ STATE_WATCHPOINTS (sd)->interrupt_names = interrupt_names;
-static void
-do_format_9_10 (insn)
- uint32 insn;
-{
- struct hash_entry *h;
+ /* Initialize the mechanism for doing insn profiling. */
+ CPU_INSN_NAME (STATE_CPU (sd, 0)) = get_insn_name;
+ CPU_MAX_INSNS (STATE_CPU (sd, 0)) = nr_itable_entries;
- h = lookup_hash (insn);
- OP[0] = insn & 0x1f;
- OP[1] = (insn >> 11) & 0x1f;
- (h->ops->func) ();
-}
+ if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
+ return 0;
-void
-sim_size (power)
- int power;
+ /* Allocate core managed memory */
-{
- if (State.mem)
- {
- free (State.mem);
- }
+ /* "Mirror" the ROM addresses below 1MB. */
+ sim_do_commandf (sd, "memory region 0,0x100000,0x%lx", V850_ROM_SIZE);
+ /* Chunk of ram adjacent to rom */
+ sim_do_commandf (sd, "memory region 0x100000,0x%lx", V850_LOW_END-0x100000);
+ /* peripheral I/O region - mirror 1K across 4k (0x1000) */
+ sim_do_command (sd, "memory region 0xfff000,0x1000,1024");
+ /* similarly if in the internal RAM region */
+ sim_do_command (sd, "memory region 0xffe000,0x1000,1024");
- State.mem = (uint8 *)calloc(1,1<<MEM_SIZE);
- if (!State.mem)
+ /* The parser will print an error message for us, so we silently return. */
+ if (sim_parse_args (sd, argv) != SIM_RC_OK)
{
- (*v850_callback->printf_filtered) (v850_callback, "Memory allocation failed.\n");
- exit(1);
+ /* Uninstall the modules to avoid memory leaks,
+ file descriptor leaks, etc. */
+ sim_module_uninstall (sd);
+ return 0;
}
-}
-static void
-init_system ()
-{
- if (!State.mem)
- sim_size(1);
-}
-
-int
-sim_write (addr, buffer, size)
- SIM_ADDR addr;
- unsigned char *buffer;
- int size;
-{
- int i;
- init_system ();
-
- for (i = 0; i < size; i++)
+ /* check for/establish the a reference program image */
+ if (sim_analyze_program (sd,
+ (STATE_PROG_ARGV (sd) != NULL
+ ? *STATE_PROG_ARGV (sd)
+ : NULL),
+ abfd) != SIM_RC_OK)
{
- State.mem[i+addr] = buffer[i];
+ sim_module_uninstall (sd);
+ return 0;
}
- return size;
-}
-void
-sim_open (args)
- char *args;
-{
- struct simops *s;
- struct hash_entry *h;
- if (args != NULL)
+ /* establish any remaining configuration options */
+ if (sim_config (sd) != SIM_RC_OK)
{
-#ifdef DEBUG
- if (strcmp (args, "-t") == 0)
- v850_debug = DEBUG;
- else
-#endif
- (*v850_callback->printf_filtered) (v850_callback, "ERROR: unsupported option(s): %s\n",args);
+ sim_module_uninstall (sd);
+ return 0;
}
- /* put all the opcodes in the hash table */
- for (s = Simops; s->func; s++)
+ if (sim_post_argv_init (sd) != SIM_RC_OK)
{
- h = &hash_table[hash(s->opcode)];
-
- /* go to the last entry in the chain */
- while (h->next)
- h = h->next;
-
- if (h->ops)
- {
- h->next = calloc(1,sizeof(struct hash_entry));
- h = h->next;
- }
- h->ops = s;
- h->mask = s->mask;
- h->opcode = s->opcode;
+ /* Uninstall the modules to avoid memory leaks,
+ file descriptor leaks, etc. */
+ sim_module_uninstall (sd);
+ return 0;
}
-}
-
-
-void
-sim_close (quitting)
- int quitting;
-{
- /* nothing to do */
-}
-void
-sim_set_profile (n)
- int n;
-{
- (*v850_callback->printf_filtered) (v850_callback, "sim_set_profile %d\n", n);
-}
-
-void
-sim_set_profile_size (n)
- int n;
-{
- (*v850_callback->printf_filtered) (v850_callback, "sim_set_profile_size %d\n", n);
-}
-void
-sim_resume (step, siggnal)
- int step, siggnal;
-{
- uint32 inst, opcode;
- reg_t oldpc;
-
- PC = State.sregs[0];
-
- if (step)
- State.exception = SIGTRAP;
- else
- State.exception = 0;
-
- do
- {
- inst = RLW (PC);
- oldpc = PC;
- opcode = (inst & 0x07e0) >> 5;
- if ((opcode & 0x30) == 0
- || (opcode & 0x38) == 0x10)
- {
- do_format_1_2 (inst & 0xffff);
- PC += 2;
- }
- else if ((opcode & 0x3C) == 0x18
- || (opcode & 0x3C) == 0x1C
- || (opcode & 0x3C) == 0x20
- || (opcode & 0x3C) == 0x24
- || (opcode & 0x3C) == 0x28)
- {
- do_format_4 (inst & 0xffff);
- PC += 2;
- }
- else if ((opcode & 0x3C) == 0x2C)
- {
- do_format_3 (inst & 0xffff);
- /* No PC update, it's done in the instruction. */
- }
- else if ((opcode & 0x38) == 0x30)
- {
- do_format_6 (inst);
- PC += 4;
- }
- else if ((opcode & 0x3C) == 0x38)
- {
- do_format_7 (inst);
- PC += 4;
- }
- else if ((opcode & 0x3E) == 0x3C)
- {
- do_format_5 (inst);
- /* No PC update, it's done in the instruction. */
- }
- else if ((opcode & 0x3F) == 0x3E)
- {
- do_format_8 (inst);
- PC += 4;
- }
- else
- {
- do_format_9_10 (inst);
- PC += 4;
- }
- }
- while (!State.exception);
-
- State.sregs[0] = PC;
-}
-
-int
-sim_trace ()
-{
-#ifdef DEBUG
- v850_debug = DEBUG;
-#endif
- sim_resume (0, 0);
- return 1;
-}
-
-void
-sim_info (verbose)
- int verbose;
-{
- (*v850_callback->printf_filtered) (v850_callback, "sim_info\n");
-}
+ /* determine the machine type */
+ if (STATE_ARCHITECTURE (sd) != NULL
+ && (STATE_ARCHITECTURE (sd)->arch == bfd_arch_v850
+ || STATE_ARCHITECTURE (sd)->arch == bfd_arch_v850_rh850))
+ mach = STATE_ARCHITECTURE (sd)->mach;
+ else
+ mach = bfd_mach_v850; /* default */
-void
-sim_create_inferior (start_address, argv, env)
- SIM_ADDR start_address;
- char **argv;
- char **env;
-{
- PC = start_address;
-}
+ /* set machine specific configuration */
+ switch (mach)
+ {
+ case bfd_mach_v850:
+ case bfd_mach_v850e:
+ case bfd_mach_v850e1:
+ case bfd_mach_v850e2:
+ case bfd_mach_v850e2v3:
+ case bfd_mach_v850e3v5:
+ STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT
+ | PSW_CY | PSW_OV | PSW_S | PSW_Z);
+ break;
+ }
+ /* CPU specific initialization. */
+ for (i = 0; i < MAX_NR_PROCESSORS; ++i)
+ {
+ SIM_CPU *cpu = STATE_CPU (sd, i);
-void
-sim_kill ()
-{
- /* nothing to do */
-}
+ CPU_REG_FETCH (cpu) = v850_reg_fetch;
+ CPU_REG_STORE (cpu) = v850_reg_store;
+ CPU_PC_FETCH (cpu) = v850_pc_get;
+ CPU_PC_STORE (cpu) = v850_pc_set;
+ }
-void
-sim_set_callbacks(p)
- host_callback *p;
-{
- v850_callback = p;
+ return sd;
}
-/* All the code for exiting, signals, etc needs to be revamped.
-
- This is enough to get c-torture limping though. */
-void
-sim_stop_reason (reason, sigrc)
- enum sim_stop *reason;
- int *sigrc;
+SIM_RC
+sim_create_inferior (SIM_DESC sd,
+ struct bfd * prog_bfd,
+ char * const *argv,
+ char * const *env)
{
-
- *reason = sim_stopped;
- if (State.exception == SIGQUIT)
- *sigrc = 0;
- else
- *sigrc = State.exception;
+ memset (&State, 0, sizeof (State));
+ if (prog_bfd != NULL)
+ PC = bfd_get_start_address (prog_bfd);
+ return SIM_RC_OK;
}
-void
-sim_fetch_register (rn, memory)
- int rn;
- unsigned char *memory;
+static int
+v850_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
- put_word (memory, State.regs[rn]);
-}
-
-void
-sim_store_register (rn, memory)
- int rn;
- unsigned char *memory;
-{
- State.regs[rn] = get_word (memory);
+ *(unsigned32*)memory = H2T_4 (State.regs[rn]);
+ return -1;
}
-int
-sim_read (addr, buffer, size)
- SIM_ADDR addr;
- unsigned char *buffer;
- int size;
+static int
+v850_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
- int i;
- for (i = 0; i < size; i++)
- {
- buffer[i] = State.mem[addr + i];
- }
- return size;
-}
-
-void
-sim_do_command (cmd)
- char *cmd;
-{
- (*v850_callback->printf_filtered) (v850_callback, "sim_do_command: %s\n", cmd);
+ State.regs[rn] = T2H_4 (*(unsigned32 *) memory);
+ return length;
}
-
-int
-sim_load (prog, from_tty)
- char *prog;
- int from_tty;
-{
- /* Return nonzero so GDB will handle it. */
- return 1;
-}
projects / binutils-gdb.git / blobdiff