#include "sim-base.h"
+#include "simops.h"
+#include "bfd.h"
+
+
typedef signed8 int8;
typedef unsigned8 uint8;
typedef signed16 int16;
reg_t sregs[32]; /* system registers, including psw */
reg_t pc;
int dummy_mem; /* where invalid accesses go */
- int pending_nmi;
} v850_regs;
struct _sim_cpu
{
/* ... simulator specific members ... */
v850_regs reg;
+ reg_t psw_mask; /* only allow non-reserved bits to be set */
+ sim_event *pending_nmi;
/* ... base type ... */
sim_cpu_base base;
};
#define SIG_V850_EXIT -1 /* indication of a normal exit */
-extern uint32 OP[4];
/* Because we are still using the old semantic table, provide compat
macro's that store the instruction where the old simops expects
it. */
+extern uint32 OP[4];
#if 0
-OP[0] = inst & 0x1f;
-OP[1] = (inst >> 11) & 0x1f;
-OP[2] = (inst >> 16) & 0xffff;
+OP[0] = inst & 0x1f; /* RRRRR -> reg1 */
+OP[1] = (inst >> 11) & 0x1f; /* rrrrr -> reg2 */
+OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */
OP[3] = inst;
#endif
-#define COMPAT_1(CALL) \
+#define SAVE_1 \
PC = cia; \
OP[0] = instruction_0 & 0x1f; \
OP[1] = (instruction_0 >> 11) & 0x1f; \
OP[2] = 0; \
-OP[3] = instruction_0 ; \
+OP[3] = instruction_0
+
+#define COMPAT_1(CALL) \
+SAVE_1; \
PC += (CALL); \
nia = PC
-#define COMPAT_2(CALL) \
+#define SAVE_2 \
PC = cia; \
OP[0] = instruction_0 & 0x1f; \
OP[1] = (instruction_0 >> 11) & 0x1f; \
OP[2] = instruction_1; \
-OP[3] = (instruction_1 << 16) | instruction_0; \
+OP[3] = (instruction_1 << 16) | instruction_0
+
+#define COMPAT_2(CALL) \
+SAVE_2; \
PC += (CALL); \
nia = PC
-#if 0
-extern struct simops Simops[];
-#endif
+/* new */
+#define GR ((CPU)->reg.regs)
+#define SR ((CPU)->reg.sregs)
+/* old */
#define State (STATE_CPU (simulator, 0)->reg)
#define PC (State.pc)
#define SP (State.regs[3])
#define ECR (State.sregs[4])
#define PSW (State.sregs[5])
/* start-sanitize-v850e */
-#define CTPC (State.sregs[16])
-#define CTPSW (State.sregs[17])
+#define CTPC (SR[16])
+#define CTPSW (SR[17])
/* end-sanitize-v850e */
#define DBPC (State.sregs[18])
#define DBPSW (State.sregs[19])
#define CTBP (State.sregs[20])
/* end-sanitize-v850e */
+/* start-sanitize-v850eq */
+#define PSW_US BIT32 (8)
+/* end-sanitize-v850eq */
#define PSW_NP 0x80
#define PSW_EP 0x40
#define PSW_ID 0x20
sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
PC, sim_core_write_map, (ADDR), (DATA))
-#include "simops.h"
+
+/* compare cccc field against PSW */
+int condition_met (unsigned code);
+
+
+/* Debug/tracing calls */
+
+enum op_types
+{
+ OP_UNKNOWN,
+ OP_NONE,
+ OP_TRAP,
+ OP_REG,
+ OP_REG_REG,
+ OP_REG_REG_CMP,
+ OP_REG_REG_MOVE,
+ OP_IMM_REG,
+ OP_IMM_REG_CMP,
+ OP_IMM_REG_MOVE,
+ OP_COND_BR,
+ OP_LOAD16,
+ OP_STORE16,
+ OP_LOAD32,
+ OP_STORE32,
+ OP_JUMP,
+ OP_IMM_REG_REG,
+ OP_UIMM_REG_REG,
+ OP_IMM16_REG_REG,
+ OP_UIMM16_REG_REG,
+ OP_BIT,
+ OP_EX1,
+ OP_EX2,
+ OP_LDSR,
+ OP_STSR,
+/* start-sanitize-v850e */
+ OP_BIT_CHANGE,
+ OP_REG_REG_REG,
+ OP_REG_REG3,
+/* end-sanitize-v850e */
+/* start-sanitize-v850eq */
+ OP_IMM_REG_REG_REG,
+ OP_PUSHPOP1,
+ OP_PUSHPOP2,
+ OP_PUSHPOP3,
+/* end-sanitize-v850eq */
+};
+
+#ifdef DEBUG
+void trace_input PARAMS ((char *name, enum op_types type, int size));
+void trace_output PARAMS ((enum op_types result));
+void trace_result PARAMS ((int has_result, unsigned32 result));
+
+extern int trace_num_values;
+extern unsigned32 trace_values[];
+extern unsigned32 trace_pc;
+extern const char *trace_name;
+extern const char *trace_module;
+
+#define TRACE_ALU_INPUT0() \
+do { \
+ if (TRACE_ALU_P (CPU)) { \
+ trace_module = "alu"; \
+ trace_pc = cia; \
+ trace_name = itable[MY_INDEX].name; \
+ trace_num_values = 0; \
+ } \
+} while (0)
+
+#define TRACE_ALU_INPUT1(IN1) \
+do { \
+ if (TRACE_ALU_P (CPU)) { \
+ trace_module = "alu"; \
+ trace_pc = cia; \
+ trace_name = itable[MY_INDEX].name; \
+ trace_values[0] = (IN1); \
+ trace_num_values = 1; \
+ } \
+} while (0)
+
+#define TRACE_ALU_INPUT2(IN1, IN2) \
+do { \
+ if (TRACE_ALU_P (CPU)) { \
+ trace_module = "alu"; \
+ trace_pc = cia; \
+ trace_name = itable[MY_INDEX].name; \
+ trace_values[0] = (IN1); \
+ trace_values[1] = (IN2); \
+ trace_num_values = 2; \
+ } \
+} while (0)
+
+#define TRACE_ALU_INPUT3(IN0, IN1, IN2) \
+do { \
+ if (TRACE_ALU_P (CPU)) { \
+ trace_module = "alu"; \
+ trace_pc = cia; \
+ trace_name = itable[MY_INDEX].name; \
+ trace_values[0] = (IN0); \
+ trace_values[1] = (IN1); \
+ trace_values[2] = (IN2); \
+ trace_num_values = 3; \
+ } \
+} while (0)
+
+#define TRACE_ALU_RESULT(RESULT) \
+do { \
+ if (TRACE_ALU_P (CPU)) { \
+ trace_result (1, (RESULT)); \
+ } \
+} while (0)
+
+#define TRACE_BRANCH0() \
+do { \
+ if (TRACE_BRANCH_P (CPU)) { \
+ trace_module = "branch"; \
+ trace_pc = cia; \
+ trace_name = itable[MY_INDEX].name; \
+ trace_num_values = 0; \
+ trace_result (1, (nia)); \
+ } \
+} while (0)
+
+#define TRACE_BRANCH1(IN1) \
+do { \
+ if (TRACE_BRANCH_P (CPU)) { \
+ trace_module = "branch"; \
+ trace_pc = cia; \
+ trace_name = itable[MY_INDEX].name; \
+ trace_values[0] = (IN1); \
+ trace_num_values = 1; \
+ trace_result (1, (nia)); \
+ } \
+} while (0)
+
+#define TRACE_BRANCH2(IN1, IN2) \
+do { \
+ if (TRACE_BRANCH_P (CPU)) { \
+ trace_module = "branch"; \
+ trace_pc = cia; \
+ trace_name = itable[MY_INDEX].name; \
+ trace_values[0] = (IN1); \
+ trace_values[1] = (IN2); \
+ trace_num_values = 2; \
+ trace_result (1, (nia)); \
+ } \
+} while (0)
+
+#define TRACE_BRANCH3(IN1, IN2, IN3) \
+do { \
+ if (TRACE_BRANCH_P (CPU)) { \
+ trace_module = "branch"; \
+ trace_pc = cia; \
+ trace_name = itable[MY_INDEX].name; \
+ trace_values[0] = (IN1); \
+ trace_values[1] = (IN2); \
+ trace_values[2] = (IN3); \
+ trace_num_values = 3; \
+ trace_result (1, (nia)); \
+ } \
+} while (0)
+
+#define TRACE_LD(ADDR,RESULT) \
+do { \
+ if (TRACE_MEMORY_P (CPU)) { \
+ trace_module = "memory"; \
+ trace_pc = cia; \
+ trace_name = itable[MY_INDEX].name; \
+ trace_values[0] = (ADDR); \
+ trace_num_values = 1; \
+ trace_result (1, (RESULT)); \
+ } \
+} while (0)
+
+/* start-sanitize-v850e */
+#define TRACE_LD_NAME(NAME, ADDR,RESULT) \
+do { \
+ if (TRACE_MEMORY_P (CPU)) { \
+ trace_module = "memory"; \
+ trace_pc = cia; \
+ trace_name = (NAME); \
+ trace_values[0] = (ADDR); \
+ trace_num_values = 1; \
+ trace_result (1, (RESULT)); \
+ } \
+} while (0)
+
+/* end-sanitize-v850e */
+#define TRACE_ST(ADDR,RESULT) \
+do { \
+ if (TRACE_MEMORY_P (CPU)) { \
+ trace_module = "memory"; \
+ trace_pc = cia; \
+ trace_name = itable[MY_INDEX].name; \
+ trace_values[0] = (ADDR); \
+ trace_num_values = 1; \
+ trace_result (1, (RESULT)); \
+ } \
+} while (0)
+
+#else
+#define trace_input(NAME, IN1, IN2)
+#define trace_output(RESULT)
+#define trace_result(HAS_RESULT, RESULT)
+
+#define TRACE_ALU_INPUT0()
+#define TRACE_ALU_INPUT1(IN0)
+#define TRACE_ALU_INPUT2(IN0, IN1)
+#define TRACE_ALU_INPUT2(IN0, IN1)
+#define TRACE_ALU_INPUT2(IN0, IN1 INS2)
+#define TRACE_ALU_RESULT(RESULT)
+
+#define TRACE_BRANCH0()
+#define TRACE_BRANCH1(IN1)
+#define TRACE_BRANCH2(IN1, IN2)
+#define TRACE_BRANCH2(IN1, IN2, IN3)
+
+#define TRACE_LD(ADDR,RESULT)
+#define TRACE_ST(ADDR,RESULT)
+
+#endif
+
+
+/* start-sanitize-v850eq */
+extern void divun ( unsigned int N,
+ unsigned long int als,
+ unsigned long int sfi,
+ unsigned long int * quotient_ptr,
+ unsigned long int * remainder_ptr,
+ boolean * overflow_ptr
+ );
+extern void divn ( unsigned int N,
+ unsigned long int als,
+ unsigned long int sfi,
+ signed long int * quotient_ptr,
+ signed long int * remainder_ptr,
+ boolean * overflow_ptr
+ );
+/* end-sanitize-v850eq */
+/* start-sanitize-v850e */
+extern int type1_regs[];
+extern int type2_regs[];
+/* end-sanitize-v850e */
+/* start-sanitize-v850eq */
+extern int type3_regs[];
+/* end-sanitize-v850eq */
projects / binutils-gdb.git / blobdiff