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[libreriscv.git] / simple_v_extension / abridged_spec.mdwn

diff --git a/simple_v_extension/abridged_spec.mdwn b/simple_v_extension/abridged_spec.mdwn
index 69c7af8c8a4ca60b47fb4daba5d3aa8e112b1c4a..1c1a180f9463b0a60d86eed8267160fce539dc16 100644 (file)
--- a/simple_v_extension/abridged_spec.mdwn
+++ b/simple_v_extension/abridged_spec.mdwn
@@ -1,3 +1,4 @@
+
 # Simple-V (Parallelism Extension Proposal) Specification (Abridged)
 
 * Copyright (C) 2017, 2018, 2019 Luke Kenneth Casson Leighton
@@ -41,12 +42,19 @@ and Register or Predicate over-ride tables may be empty: under such
 circumstances the behaviour becomes effectively identical to standard
 RV execution, however SV is never truly actually "off".
 
-Note: **there are *no* new opcodes**. The scheme works *entirely*
+Note: **there are *no* new vector opcodes**. The scheme works *entirely*
 on hidden context that augments (nests) *scalar* RISC-V instructions.
 Thus it may cover existing, future and custom scalar extensions, turning
 all existing, all future and all custom scalar operations parallel,
 without requiring any special (identical, parallel variant) opcodes to do so.
 
+Associated proposals for use with 3D and HPC:
+
+* [[specification/sv.setvl]] - replaces the use of CSRs to set VL (saves
+  32 bits)
+* [[specification/mv.x]] - provides MV.swizzle and MVX (reg[rd] = reg[reg[rs]])
+* [[ztrans_proposal]] - provides trigonometric and transcendental operations
+
 # CSRs <a name="csrs"></a>
 
 There are five CSRs, available in any privilege level:
@@ -226,6 +234,11 @@ Pseudocode for predication:
 The swizzle table is a key-value store that indicates (if a given
 register is used, and SUBVL is 2, 3 or 4) that the sub-elements are to
 be re-ordered according to the indices in the Swizzle format.
+Like the Predication Table, it is an indirect lookup: use of a
+source or destination register in any given operation, if that register
+occurs in the table, "activates" sub-vector element swizzling for
+that register.  Note that the target is taken from the "Register Table"
+(regidx).
 
 Source vectors are free to have the swizzle indices point to the same
 sub-vector element.  However when using swizzling on destination vectors,
@@ -235,15 +248,27 @@ if this occurs.
 
 [[!inline raw="yes" pages="simple_v_extension/swizzle_table_format" ]]
 
-Pseudocode when SUBVL=4 and swizzle is set on rd:
+Simplified pseudocode example, when SUBVL=4 and swizzle is set on rd:
+
+    # default indices if no swizzling table entry present
+    x, y, z, w = 0, 1, 2, 3
+
+    # lookup swizzling in table for rd
+    if swizzle_table[rd].active:
+        swizzle = swizzle_table[rd].swizzle
+
+        # decode the swizzle table entry for rd
+        x = swizzle[0:1] # sub-element 0
+        y = swizzle[2:3] # sub-element 1
+        z = swizzle[4:5] # sub-element 2
+        w = swizzle[6:7] # sub-element 3
 
-    # decode the swizzle table entry for rd
-    x = swizzle[0:1] # sub-element 0
-    y = swizzle[2:3] # sub-element 1
-    z = swizzle[4:5] # sub-element 2
-    w = swizzle[6:7] # sub-element 3
+    # redirect register numbers through Register Table
+    rd  = int_vec[rd ].isvector ? int_vec[rd ].regidx : rd;
+    rs1 = int_vec[rs1].isvector ? int_vec[rs1].regidx : rs1;
+    rs2 = int_vec[rs2].isvector ? int_vec[rs2].regidx : rs2;
 
-    # loop on VL: SUBVL loop is unrolled
+    # loop on VL: SUBVL loop is unrolled (SUBVL=4)
     for (i in 0; i < VL; i++)
         ireg[rd+i*4+x] = OPERATION(ireg[rs1+i*4+0], ireg[rs2+i*4+0])
         ireg[rd+i*4+y] = OPERATION(ireg[rs1+i*4+1], ireg[rs2+i*4+1])