(no commit message)

[libreriscv.git] / simple_v_extension / abridged_spec.mdwn

diff --git a/simple_v_extension/abridged_spec.mdwn b/simple_v_extension/abridged_spec.mdwn
index 0990d0d0d06be8d23b8061f46c3d80143bb23dc7..1c1a180f9463b0a60d86eed8267160fce539dc16 100644 (file)
--- a/simple_v_extension/abridged_spec.mdwn
+++ b/simple_v_extension/abridged_spec.mdwn
@@ -1,3 +1,4 @@
+
 # Simple-V (Parallelism Extension Proposal) Specification (Abridged)
 
 * Copyright (C) 2017, 2018, 2019 Luke Kenneth Casson Leighton
@@ -49,8 +50,9 @@ without requiring any special (identical, parallel variant) opcodes to do so.
 
 Associated proposals for use with 3D and HPC:
 
-* [[sv.setvl]] - replaces the use of CSRs to set VL (saves 32 bits)
-* [[mv.x]] - provides MV.swizzle and MVX (reg[rd] = reg[reg[rs]])
+* [[specification/sv.setvl]] - replaces the use of CSRs to set VL (saves
+  32 bits)
+* [[specification/mv.x]] - provides MV.swizzle and MVX (reg[rd] = reg[reg[rs]])
 * [[ztrans_proposal]] - provides trigonometric and transcendental operations
 
 # CSRs <a name="csrs"></a>