move vector block format. clarify exceptions

[libreriscv.git] / simple_v_extension / abridged_spec.mdwn

diff --git a/simple_v_extension/abridged_spec.mdwn b/simple_v_extension/abridged_spec.mdwn
index 9cf284f448cd59f816263474a86433c6754d36d3..5032eb51a63024ab29b4f682ec914b27314837f5 100644 (file)
--- a/simple_v_extension/abridged_spec.mdwn
+++ b/simple_v_extension/abridged_spec.mdwn
@@ -239,9 +239,24 @@ to be set.
 
 See [[appendix]] for more details on fail-on-first modes.
 
+# Vector Block Format <a name="vliw-format"></a>
+
+The Vector Block format uses the RISC-V 80-192 bit format from Section 1.5
+of the RISC-V Spec.  It permits an optional VL/MVL/SUBVL block, up to 4
+16-bit (or 8 8-bit) Register Table entries, the same for Predicate Entries,
+and the rest of the instruction may be either standard RV opcodes or the
+SVPrefix opcodes ([[sv_prefix_proposal]])
+
+[[!inline raw="yes" pages="simple_v_extension/vblock_format_table" ]]
+
+For full details see ancillary resource: [[vblock_format]]
+
 # Exceptions
 
-TODO: expand.  
+Exception handling **MUST** be precise, in-order, and exactly
+like Standard RISC-V as far as the instruction execution order is
+concerned, regardless of whether it is PC, PCVBLK, VL or SUBVL that
+is currently being incremented.
 
 # Hints
 
@@ -253,18 +268,6 @@ in as a *parameter* to the HINT operation.
 
 No specific hints are yet defined in Simple-V
 
-# Vector Block Format <a name="vliw-format"></a>
-
-The Vector Block format uses the RISC-V 80-192 bit format from Section 1.5
-of the RISC-V Spec.  It permits an optional VL/MVL/SUBVL block, up to 4
-16-bit (or 8 8-bit) Register Table entries, the same for Predicate Entries,
-and the rest of the instruction may be either standard RV opcodes or the
-SVPrefix opcodes ([[sv_prefix_proposal]])
-
-[[!inline raw="yes" pages="simple_v_extension/vblock_format_table" ]]
-
-For full details see ancillary resource: [[vblock_format]]
-
 # Subsets of RV functionality
 
 It is permitted to only implement SVprefix and not the VBLOCK instruction