bug 1220: add a few more slides with examples

[libreriscv.git] / simple_v_extension / appendix.mdwn

diff --git a/simple_v_extension/appendix.mdwn b/simple_v_extension/appendix.mdwn
index d4a69b3529a925f146827c1de1449e46abd8cb65..c29044cfea6b9772be22c43d9b8dc3d968f819ee 100644 (file)
--- a/simple_v_extension/appendix.mdwn
+++ b/simple_v_extension/appendix.mdwn
@@ -1,6 +1,8 @@
-[[!tag standards]]
+[[!oldstandards]]
 
-# Simple-V (Parallelism Extension Proposal) Appendix
+# Simple-V (Parallelism Extension Proposal) Appendix (OBSOLETE)
+
+**OBSOLETE**
 
 * Copyright (C) 2017, 2018, 2019 Luke Kenneth Casson Leighton
 * Status: DRAFTv0.6
@@ -1098,7 +1100,7 @@ Note:
   is also marked as scalar, this is how the compatibility with
   standard RV LOAD/STORE is preserved by this algorithm.
 
-### Example Tables showing LOAD elements
+### Example Tables showing LOAD elements <a name="load_example"></a>
 
 This section contains examples of vectorised LOAD operations, showing
 how the two stage process works (three if zero/sign-extension is included).
@@ -1458,7 +1460,7 @@ circumstances it is perfectly fine to simply have the lanes
 "inactive" for predicated elements, even though it results in
 less than 100% ALU utilisation.
 
-## Twin-predication (based on source and destination register)
+## Twin-predication (based on source and destination register) <a name="tpred"></a>
 
 Twin-predication is not that much different, except that that
 the source is independently zero-predicated from the destination.