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[libreriscv.git] / simple_v_extension / bigint_example.mdwn

diff --git a/simple_v_extension/bigint_example.mdwn b/simple_v_extension/bigint_example.mdwn
index d2673e32c0cfec47640fdb34cdc850b19ec7273e..17133bd1fc805f9a179c00399660c7e9fca3b94d 100644 (file)
--- a/simple_v_extension/bigint_example.mdwn
+++ b/simple_v_extension/bigint_example.mdwn
@@ -3,21 +3,25 @@
     VBLK.pred.t4 = {t0 }
     VBLK.reg.a0 = {vec}
     VBLK.reg.a1 = {vec}
+    VBLK.reg.t4 = {vec}
     VBLK.VL = 8
-    add t4, a0, a1
-    sub t3, x0, a1 # invert a1
-    BLT a0, t3, cont # stores tests in t0
-    ret
-
+    {
+     add t4, a0, a1 # vector add of int64
+     sub t3, x0, a1 # invert a1
+     BLT a0, t3, cont # stores tests in t0
+     c.ret
+    }
     VBLK.pred.t1 = {inv, t0}
-    VBLK.pred.t4 = {t0 }
-    VBLK.reg.a0 = {vec}
-    VBLK.reg.a1 = {vec}
-    cont:
-    slli t0, 1 # shifts up carry by 1
-    addi t4, 1 # predicated on t0
-    BLT t4, t1, cont2 # tests into t0
-    ret
-    cont2:
-    j cont
+    VBLK.pred.t4 = {t0}
+    VBLK.reg.t4 = {vec}
+    VBLK.VL = 8
+    {
+     cont:
+     c.slli t0, 1 # shifts up carry by 1
+     c.addi t4, 1 # predicated on t0
+     BLT t4, t1, cont2 # tests into t0
+     c.ret
+     cont2:
+     c.j cont
+    }