# SimpleV Instruction Categorisation
-Based on information from Michael Clark's riscv-meta opcodes table, this
+Based on information from Michael Clark's riscv-meta opcodes table
+(with thanks to Michael for creating it), this
page categorises and identifies the type of parallelism that SimpleV
indirectly adds on each RISC-V **standard** opcode. These are note-form:
see [[specification]] for full details.
+Note that the list is necessarily incomplete, as any custom or future
+extensions may also benefit from fitting one of the categories below.
+
* **-** no change of behaviour takes place: operation remains
**completely scalar** as an **unmodified**, unaugmented standard RISC-V
opcode, even if it has registers.
indirected) twin-register operation (distinct source and destination)
where either or both of source or destination may be redirected,
vectorised, or **independently** predicated. This behaviour
- covers the *entire* MV, VSPLAT, VINSERT, VREDUCE, VSCATTER, VGATHER
+ covers the *entire* VMV, VSPLAT, VINSERT, VREDUCE, VSCATTER, VGATHER
paradigm.
* **vld** - a standard contiguous (optionally twin-predicated, optionally
indirected) multi-register load operation where either or both of
|flt.d | rd frs1 frs2 | r+rff | rv32d rv64d rv128d | sv |
|feq.d | rd frs1 frs2 | r+rff | rv32d rv64d rv128d | sv |
|fclass.d | rd frs1 | r+rf | rv32d rv64d rv128d | sv |
+| | | | | |
|fsgnj.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | 2v |
|fsgnjn.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | 2v |
|fsgnjx.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | 2v |