# SimpleV Instruction Categorisation
-Based on information from Michael Clark's riscv-meta opcodes table, this
+Based on information from Michael Clark's riscv-meta opcodes table
+(with thanks to Michael for creating it), this
page categorises and identifies the type of parallelism that SimpleV
indirectly adds on each RISC-V **standard** opcode. These are note-form:
see [[specification]] for full details.
+Note that the list is necessarily incomplete, as any custom or future
+extensions may also benefit from fitting one of the categories below.
+
* **-** no change of behaviour takes place: operation remains
**completely scalar** as an **unmodified**, unaugmented standard RISC-V
opcode, even if it has registers.