\frame{\frametitle{Libre RISC-V Team}
\begin{itemize}
- \item Small team, sponsored by Purism and the NLNet Foundation\vspace{8pt}
+ \item Small team, sponsored by Purism and the NLnet Foundation\vspace{8pt}
\item Therefore, focus is on efficiency: leap-frogging ahead\\
without requiring huge resources.\vspace{8pt}
\item OpenGL API? Gallium3D / Vulkan is better\vspace{8pt}
\item Decided to go the "Hybrid" Route (Separate GPUs requires a\\
full-blown RPC/IPC mechanism to transfer all 3D API calls\\
to and from userspace memory to GPU memory... and back).
- \item Developed Simple-V (a "Parallelising API)\\
+ \item Developed Simple-V (a "Parallelising" API)\\
(Simple-V is very hard to describe, because it is unique:\\
there is no common Computer Science terminology)
\item Started on Kazan (a Vulkan SPIR-V to LLVM compiler)
with help from Mitch Alsup, the designer of the M68000
\item Variable-issue, predicated SIMD backend, Vector front-end\\
"precise" exceptions, branch shadowing, much more
+ \item All Libre-licensed and developed publicly and transparently.
\end{itemize}
}
\begin{itemize}
\item RVV is designed exclusively for supercomputing\\
- (RVV simply has not been designed with 3D in mind).\vspace{6pt}
+ (RVV simply has not been designed with 3D in mind).
\item Like SIMD, RVV uses dedicated opcodes\\
- (google "SIMD considered harmful")\vspace{6pt}
+ (google "SIMD considered harmful")
\item 98\% of FP opcodes are duplicated in RVV. Large portion\\
- of BitManip opcodes duplicated in predicate Masks\vspace{6pt}
+ of BitManip opcodes duplicated in predicate Masks
\item OP32 space is extremely precious: 48 and 64 bit opcode space\\
- comes with an inherent I-Cache power consumption penalty\vspace{6pt}
+ comes with an inherent I-Cache power consumption penalty
\item Simple-V "prefixes" scalar opcodes (all of them)\\
No need for any new "vector" opcodes (at all).\\
- Can therefore use the RVV major opcode for 3D\vspace{6pt}
+ Can therefore use the RVV major opcode for 3D
+ \item SV augments "scalar" opcodes. Implications: it is relatively\\
+ straightforward to convert an \textit{existing design} to SV.\\
+ SV "slots in" between instruction decode and the ALU.
\end{itemize}
}
\item With a custom specialised SPIR-V (Vulkan) Compiler\\
being an absolutely critical strategic requirement,\\
RVV and its associated compiler (still not developed)\\
- is, surprisingly, of marginal value.
+ is of marginal value (no clear benefits, extra cost)
\item Question everything! Your input, and a willingness to\\
take active responsibility for tasks that your Company\\
is critically dependent on, are extremely important.