\begin{itemize}
\item Hybrid - integrated. The CPU \textit{is} the GPU.\\
The GPU \textit{is} the CPU. The VPU \textit{is} the CPU.\\
- \textit{There is No Separate VPU/GPU Pipeline}
+ \textit{There is No Separate VPU/GPU Pipeline}\\
\vspace{9pt}
\item written in nmigen (a python-based HDL). Not VHDL\\
not Verilog (definitely not Chisel3/Scala)\\
\begin{itemize}
\item CDC 6600 is a design from 1965. The \textit{augmentations} are not.\\
- Help from Mitch Alsup includes "precise exceptions", \\
+ Help from Mitch Alsup includes \textit{precise exceptions}, \\
multi-issue and more. Academic literature on 6600 utterly misleading.
- 6600 Scoreboards completely underestimated.
+ 6600 Scoreboards completely underestimated (Seymour Cray and
+ James Thornton
+ solved problems they didn't realise existed elsewhere!)
\item Front-end Vector ISA, back-end "Predicated (masked) SIMD"\\
nmigen (python OO) strategically critical to achieving this.
\item Out-of-order combined with Simple-V allows scalar operations\\
\end{itemize}
}
+\frame{\frametitle{Why nmigen? (but first: evaluate other HDLs)}
+
+ \begin{itemize}
+ \item Verilog: designed in the 1980s purely for doing unit tests (!)
+ \item VHDL: again, a 1980s-era "Procedural" language (BASIC, Fortran).
+ Does now have "records" which is nice.
+ \item Chisel3 / Scala: OO, but very obscure (20th on index)
+ \item pyrtl: not large enough community
+ \item MyHDL: subset of python only
+ \vspace{9pt}
+ \item Slowly forming a set of criteria: must be OO (python), must have
+ wide adoption (python), must have good well-established
+ programming practices already in place (python), must be
+ easy to learn (python)
+ \item HDL itself although a much smaller community must have the same
+ criteria. Only nmigen meets that criteria.
+
+ \end{itemize}
+}
+
+\frame{\frametitle{Why nmigen?}
+
+ \begin{itemize}
+ \item Uses python to build an AST (Abstract Syntax Tree).
+ Actually hands that over to yosys (to create ILANG file)
+ after which verilog can (if necessary) be created
+ \item Deterministic synthesiseable behaviour (Signals are declared
+ with their reset pattern: no more forgetting "if rst" block).
+ \item python OO programming techniques can be deployed. classes
+ and functions created which pass in parameters which change
+ what HDL is created (IEEE754 FP16 / 32 / 64 for example)
+ \item python-based for-loops can e.g. read CSV files then generate
+ a hierarchical nested suite of HDL Switch / Case statements
+ (this is how the Libre-soc PowerISA decoder is implemented)
+ \item extreme OO abstraction can even be used to create "dynamic
+ partitioned Signals" that have the same operator-overloaded
+ "add", "subtract", "greater-than" operators
+
+ \end{itemize}
+}
+
+\frame{\frametitle{nmigen (dynamic) vs VHDL (static)}
+
+\begin{center}
+\includegraphics[width=1.0\textwidth]{2020-09-10_11-53.png}
+\end{center}
+
+}
+
+\frame{\frametitle{nmigen PowerISA Decoder}
+
+\begin{center}
+\includegraphics[width=1.0\textwidth]{2020-09-10_11-46.png}
+\end{center}
+
+}
+
+\frame{\frametitle{nmigen PowerISA Decoder}
+
+\begin{center}
+\includegraphics[width=0.55\textwidth]{2020-09-09_21-04.png}
+\end{center}
+
+}
+
+\frame{\frametitle{Why another Vector ISA? (or: not-exactly another)}
+
+ \begin{itemize}
+ \item Simple-V is a 'register tag' system. \textit{There are no opcodes}\\
+ SV 'tags' scalar operations (scalar regfiles) as 'vectorised'
+ \item (PowerISA SIMD is around 700 opcodes, making it unlikely to be
+ able to fit a PowerISA decoder in only one clock cycle)
+ \item Effectively a 'hardware sub-counter for-loop': pauses the PC\\
+ then rolls incrementally through the operand register numbers\\
+ issuing \textit{multiple} scalar instructions into the pipelines\\
+ (hence the reason for a multi-issue OoO microarchitecture)
+ \item Current \textit{and future} PowerISA scalar opcodes inherently
+ \textit{and automatically} become 'vectorised' by SV without
+ needing an explicit new Vector opcode.
+ \item Predication and element width polymorphism are also 'tags'.
+ elwidth polymorphism allows for FP16 / 80 / 128 to be added to
+ the ISA \textit{without modifying the ISA}
+
+ \end{itemize}
+}
+
+
+\begin{frame}[fragile]
+\frametitle{Simple-V ADD in a nutshell}
+
+\begin{semiverbatim}
+function op\_add(rd, rs1, rs2, predr) # add not VADD!
+ int i, id=0, irs1=0, irs2=0;
+ for (i = 0; i < VL; i++)
+ if (ireg[predr] & 1<<i) # predication uses intregs
+ ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
+ if (reg\_is\_vectorised[rd] ) \{ id += 1; \}
+ if (reg\_is\_vectorised[rs1]) \{ irs1 += 1; \}
+ if (reg\_is\_vectorised[rs2]) \{ irs2 += 1; \}
+\end{semiverbatim}
+
+ \begin{itemize}
+ \item Above is oversimplified: Reg. indirection left out (for clarity).
+ \item SIMD slightly more complex (case above is elwidth = default)
+ \item Scalar-scalar and scalar-vector and vector-vector now all in one
+ \item OoO may choose to push ADDs into instr. queue (v. busy!)
+ \end{itemize}
+\end{frame}
+
\frame{\frametitle{Summary}
\begin{itemize}
- \item Actually about parallelism, not Vectors (or SIMD) per se\\
- and NOT about adding new ALU/logic/functionality.
+ \item Goal is to create a mass-volume low-power embedded SoC suitable
+ for use in netbooks, chromebooks, tablets, smartphones, IoT SBCs.
+ \item No DRM. 'Trustable' (by the users, not by Media Moguls) design
+ ethos as a \textit{business} objective: requires full transparency
+ as well as Formal Correctness Proofs
+ \item Collaboration with OpenPOWER Foundation and Members absolutely
+ essential. No short-cuts. Standards to be developed and ratified
+ so that everyone benefits.
+ \item Working on the back of huge stability of POWER ecosystem
+ \item Combination of which is that Board Support Package is 100\%
+ upstream, app and product development by customer is hugely
+ simplified and much more attractive
+
\end{itemize}
}
projects / libreriscv.git / blobdiff