clarify

[libreriscv.git] / simple_v_extension / simple_v_chennai_2018.tex

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 22142259f44ed43f8658e06d091a0bbbdc5bbd3d..79730673cf1cfe3779537efca3817b79ac8dd36b 100644 (file)
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -82,7 +82,8 @@
                 of pipeline setup, amount of state to context switch
                 and software portability\vspace{4pt}
    \item How?
-            By implicitly marking INT/FP regs as "Vectorised",\\
+            By marking INT/FP regs as "Vectorised" and
+            adding a level of indirection,
             SV expresses how existing instructions should act 
             on [contiguous] blocks of registers, in parallel.\vspace{4pt}
    \item What?
@@ -133,7 +134,8 @@
 \frame{\frametitle{How is Parallelism abstracted in Simple-V?}
 
  \begin{itemize}
-   \item Register "typing" turns any op into an implicit Vector op\vspace{10pt}
+   \item Register "typing" turns any op into an implicit Vector op:\\
+         registers are reinterpreted through a level of indirection
    \item Primarily at the Instruction issue phase (except SIMD)\\
          Note: it's ok to pass predication through to ALU (like SIMD)
    \item Standard (and future, and custom) opcodes now parallel\vspace{10pt}
@@ -347,7 +349,7 @@ for (int i = 0; i < VL; ++i)
   Considerations:
   \begin{itemize}
    \item Complex not really impacted, simple impacted a LOT\\
-         with Zeroing... however it's useful (memset)
+         with Zeroing... however it's useful (memzero)
    \item Non-zero'd overlapping "Vectors" may issue overlapping ops\\
             (2nd op's predicated elements slot in 1st's non-predicated ops)
    \item Please don't use Vectors for "security" (use Sec-Ext)
@@ -379,6 +381,30 @@ for (int i = 0; i < VL; ++i)
 }
 
 
+\begin{frame}[fragile]
+\frametitle{Predication key-value CSR table decoding pseudocode}
+
+\begin{semiverbatim}
+struct pred fp_pred[32];
+struct pred int_pred[32];
+
+for (i = 0; i < 16; i++) // 16 CSRs?
+   tb = int\_pred if CSRpred[i].type == 0 else fp\_pred
+   idx = CSRpred[i].regidx
+   tb[idx].zero     = CSRpred[i].zero
+   tb[idx].inv      = CSRpred[i].inv
+   tb[idx].predidx  = CSRpred[i].predidx
+   tb[idx].enabled  = true
+\end{semiverbatim}
+
+ \begin{itemize}
+   \item Entries zero'd before setting
+   \item Might be a bit complex to set up (TBD)
+  \end{itemize}
+
+\end{frame}
+
+
 \frame{\frametitle{Register key-value CSR store}
 
  \begin{itemize}
@@ -396,6 +422,14 @@ for (int i = 0; i < VL; ++i)
 }
 
 
+\frame{\frametitle{Register key-value CSR pseudocode}
+
+ \begin{itemize}
+   \item TODO
+  \end{itemize}
+}
+
+
 \frame{\frametitle{C.MV extremely flexible!}
 
  \begin{itemize}