add images

[libreriscv.git] / simple_v_extension / simple_v_chennai_2018.tex

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index dca373267879eb6ec11e1c1ffd7ba4ec13ab4701..993741313f492eea9300f6ca12cceb847f2486eb 100644 (file)
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -96,14 +96,17 @@
 \frame{\frametitle{What's the value of SV? Why adopt it even in non-V?}
 
  \begin{itemize}
-   \item memcpy becomes much smaller (higher bang-per-buck)\vspace{10pt}
-   \item context-switch (LOAD/STORE multiple): 1-2 instructions\vspace{10pt}
-   \item Compressed instrs further reduces I-cache (etc.)\vspace{10pt}
-   \item greatly-reduced I-cache load (and less reads)\vspace{10pt}
-  \end{itemize}
-  Note:\vspace{10pt}
+   \item memcpy becomes much smaller (higher bang-per-buck)
+   \item context-switch (LOAD/STORE multiple): 1-2 instructions
+   \item Compressed instrs further reduces I-cache (etc.)
+   \item Greatly-reduced I-cache load (and less reads)
+   \item Amazingly, SIMD becomes (more) tolerable\\
+            (corner-cases for setup and teardown are gone)
+  \end{itemize}
+  Note:
    \begin{itemize}
    \item It's not just about Vectors: it's about instruction effectiveness
+   \item Anything that makes SIMD tolerable has to be a good thing
    \item Anything implementor is not interested in HW-optimising,\\
             let it fall through to exceptions (implement as a trap).
   \end{itemize}
@@ -313,10 +316,12 @@ for (int i = 0; i < VL; ++i)
 \frame{\frametitle{Why are overlaps allowed in Regfiles?}
 
  \begin{itemize}
-   \item Same register(s) can have multiple "interpretations"\vspace{6pt}
-   \item xBitManip plus SIMD plus xBitManip = Hi/Lo bitops\vspace{6pt}
-   \item (32-bit GREV plus 4x8-bit SIMD plus 32-bit GREV)\vspace{6pt}
-   \item RGB 565 (video): BEXTW plus 4x8-bit SIMD plus BDEPW\vspace{6pt}
+   \item Same register(s) can have multiple "interpretations"
+   \item xBitManip plus SIMD plus xBitManip = Hi/Lo bitops
+   \item (32-bit GREV plus 4x8-bit SIMD plus 32-bit GREV:\\
+            GREV @ VL=N,wid=32; SIMD @ VL=Nx4,wid=8)
+   \item RGB 565 (video): BEXTW plus 4x8-bit SIMD plus BDEPW\\
+            (BEXT/BDEP @ VL=N,wid=32; SIMD @ VL=Nx4,wid=8)
    \item Same register(s) can be offset (no need for VSLIDE)\vspace{6pt}
   \end{itemize}
   Note:\vspace{10pt}
@@ -389,16 +394,17 @@ for (int i = 0; i < VL; ++i)
 \frame{\frametitle{C.MV extremely flexible!}
 
  \begin{itemize}
-   \item scalar-to-vector (w/no pred): VSPLAT
-   \item scalar-to-vector (w/dest-pred): Sparse VSPLAT
-   \item scalar-to-vector (w/single dest-pred): VINSERT
-   \item vector-to-scalar (w/src-pred): VEXTRACT
-   \item vector-to-vector (w/no pred): Vector Copy
-   \item vector-to-vector (w/src xor dest pred): Sparse Vector Copy
-   \item vector-to-vector (w/src and dest pred): Vector Gather/Scatter
-  \end{itemize}
-  \vspace{8pt}
-  Notes:\vspace{10pt}
+   \item scalar-to-vector (w/ no pred): VSPLAT
+   \item scalar-to-vector (w/ dest-pred): Sparse VSPLAT
+   \item scalar-to-vector (w/ 1-bit dest-pred): VINSERT
+   \item vector-to-scalar (w/ src-pred): VEXTRACT
+   \item vector-to-vector (w/ no pred): Vector Copy
+   \item vector-to-vector (w/ src pred): Vector Gather
+   \item vector-to-vector (w/ dest pred): Vector Scatter
+   \item vector-to-vector (w/ src \& dest pred): Vector Gather/Scatter
+  \end{itemize}
+  \vspace{4pt}
+  Notes:
    \begin{itemize}
    \item Really powerful!
    \item Any other options?
@@ -431,8 +437,6 @@ for (int i = 0; i < VL; ++i)
    \item Can VSELECT be removed? (it's really complex)
    \item Can CLIP be done as a CSR (mode, like elwidth)
    \item SIMD saturation (etc.) also set as a mode?
-   \item C.MV src predication no different from dest predication\\
-         What to do? Make one have different meaning?
    \item 8/16-bit ops is it worthwhile adding a "start offset"? \\
          (a bit like misaligned addressing... for registers)\\
          or just use predication to skip start?