of pipeline setup, amount of state to context switch
and software portability\vspace{4pt}
\item How?
- By implicitly marking INT/FP regs as "Vectorised",\\
+ By marking INT/FP regs as "Vectorised" and
+ adding a level of indirection,
SV expresses how existing instructions should act
on [contiguous] blocks of registers, in parallel.\vspace{4pt}
\item What?
\frame{\frametitle{How is Parallelism abstracted in Simple-V?}
\begin{itemize}
- \item Register "typing" turns any op into an implicit Vector op\vspace{10pt}
+ \item Register "typing" turns any op into an implicit Vector op:\\
+ registers are reinterpreted through a level of indirection
\item Primarily at the Instruction issue phase (except SIMD)\\
Note: it's ok to pass predication through to ALU (like SIMD)
\item Standard (and future, and custom) opcodes now parallel\vspace{10pt}
\item Predication in INT regs as a BIT field (max VL=XLEN)
\item Minimum VL must be Num Regs - 1 (all regs single LD/ST)
\item SV may condense sparse Vecs: RVV lets ALU do predication
- \item NO ZEROING: non-predicated elements are skipped
+ \item Choice to Zero or skip non-predicated elements
\end{itemize}
}
\frametitle{ADD pseudocode (or trap, or actual hardware loop)}
\begin{semiverbatim}
-function op_add(rd, rs1, rs2, predr) # add not VADD!
+function op\_add(rd, rs1, rs2, predr) # add not VADD!
int i, id=0, irs1=0, irs2=0;
for (i = 0; i < VL; i++)
if (ireg[predr] & 1<<i) # predication uses intregs
ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
- if (reg_is_vectorised[rd]) \{ id += 1; \}
- if (reg_is_vectorised[rs1]) \{ irs1 += 1; \}
- if (reg_is_vectorised[rs2]) \{ irs2 += 1; \}
+ if (reg\_is\_vectorised[rd]) \{ id += 1; \}
+ if (reg\_is\_vectorised[rs1]) \{ irs1 += 1; \}
+ if (reg\_is\_vectorised[rs2]) \{ irs2 += 1; \}
\end{semiverbatim}
\begin{itemize}
+ \item Above is oversimplified: Reg. indirection left out (for clarity).
\item SIMD slightly more complex (case above is elwidth = default)
\item Scalar-scalar and scalar-vector and vector-vector now all in one
\item OoO may choose to push ADDs into instr. queue (v. busy!)
\frametitle{Predication-Branch (or trap, or actual hardware loop)}
\begin{semiverbatim}
-s1 = reg_is_vectorised(src1);
-s2 = reg_is_vectorised(src2);
+s1 = reg\_is\_vectorised(src1);
+s2 = reg\_is\_vectorised(src2);
if (!s2 && !s1) goto branch;
for (int i = 0; i < VL; ++i)
if cmp(s1 ? reg[src1+i] : reg[src1],
if (unit-strided) stride = elsize;
else stride = areg[as2]; // constant-strided
for (int i = 0; i < VL; ++i)
- if (preg_enabled[rd] && ([!]preg[rd] & 1<<i))
+ if (preg\_enabled[rd] && ([!]preg[rd] & 1<<i))
for (int j = 0; j < seglen+1; j++)
- if (reg_is_vectorised[rs2]) offs = vreg[rs2+i]
+ if (reg\_is\_vectorised[rs2]) offs = vreg[rs2+i]
else offs = i*(seglen+1)*stride;
vreg[rd+j][i] = mem[sreg[base] + offs + j*stride]
\end{semiverbatim}
\begin{itemize}
\item Same register(s) can have multiple "interpretations"
+ \item Set "real" register (scalar) without needing to set/unset CSRs.
\item xBitManip plus SIMD plus xBitManip = Hi/Lo bitops
\item (32-bit GREV plus 4x8-bit SIMD plus 32-bit GREV:\\
GREV @ VL=N,wid=32; SIMD @ VL=Nx4,wid=8)
(BEXT/BDEP @ VL=N,wid=32; SIMD @ VL=Nx4,wid=8)
\item Same register(s) can be offset (no need for VSLIDE)\vspace{6pt}
\end{itemize}
- Note:\vspace{10pt}
+ Note:
\begin{itemize}
\item xBitManip reduces O($N^{6}$) SIMD down to O($N^{3}$)
\item Hi-Performance: Macro-op fusion (more pipeline stages?)
}
-\frame{\frametitle{Why no Zeroing (place zeros in non-predicated elements)?}
+\frame{\frametitle{To Zero or not to place zeros in non-predicated elements?}
\begin{itemize}
- \item Zeroing is an implementation optimisation favouring OoO\vspace{8pt}
- \item Simple implementations may skip non-predicated operations\vspace{8pt}
- \item Simple implementations explicitly have to destroy data\vspace{8pt}
+ \item Zeroing is an implementation optimisation favouring OoO
+ \item Simple implementations may skip non-predicated operations
+ \item Simple implementations explicitly have to destroy data
\item Complex implementations may use reg-renames to save power\\
Zeroing on predication chains makes optimisation harder
+ \item Compromise: REQUIRE both (specified in predication CSRs).
\end{itemize}
- Considerations:\vspace{10pt}
+ Considerations:
\begin{itemize}
- \item Complex not really impacted, Simple impacted a LOT
- \item Overlapping "Vectors" may issue overlapping ops
+ \item Complex not really impacted, simple impacted a LOT\\
+ with Zeroing... however it's useful (memzero)
+ \item Non-zero'd overlapping "Vectors" may issue overlapping ops\\
+ (2nd op's predicated elements slot in 1st's non-predicated ops)
\item Please don't use Vectors for "security" (use Sec-Ext)
\end{itemize}
}
\item key is int regfile number or FP regfile number (1 bit)\vspace{6pt}
\item register to be predicated if referred to (5 bits, key)\vspace{6pt}
\item register to store actual predication in (5 bits, value)\vspace{6pt}
- \item predication is inverted (1 bit)\vspace{6pt}
- \item non-predicated elements are to be zero'd (1 bit)\vspace{6pt}
+ \item predication is inverted Y/N (1 bit)\vspace{6pt}
+ \item non-predicated elements are to be zero'd Y/N (1 bit)\vspace{6pt}
\end{itemize}
Notes:\vspace{10pt}
\begin{itemize}
}
+\begin{frame}[fragile]
+\frametitle{Predication key-value CSR table decoding pseudocode}
+
+\begin{semiverbatim}
+struct pred fp\_pred[32];
+struct pred int\_pred[32];
+
+for (i = 0; i < 16; i++) // 16 CSRs?
+ tb = int\_pred if CSRpred[i].type == 0 else fp\_pred
+ idx = CSRpred[i].regidx
+ tb[idx].zero = CSRpred[i].zero
+ tb[idx].inv = CSRpred[i].inv
+ tb[idx].predidx = CSRpred[i].predidx
+ tb[idx].enabled = true
+\end{semiverbatim}
+
+ \begin{itemize}
+ \item All 64 (int and FP) Entries zero'd before setting
+ \item Might be a bit complex to set up (TBD)
+ \end{itemize}
+
+\end{frame}
+
+
+\begin{frame}[fragile]
+\frametitle{Get Predication value pseudocode}
+
+\begin{semiverbatim}
+def get\_pred\_val(bool is\_fp\_op, int reg):
+ tb = int\_pred if is\_fp\_op else fp\_pred
+ if (!tb[reg].enabled):
+ return ~0x0 // all ops enabled
+ predidx = tb[reg].predidx // redirection occurs HERE
+ predicate = intreg[predidx] // actual predicate HERE
+ if (tb[reg].inv):
+ predicate = ~predicate
+ return predicate
+\end{semiverbatim}
+
+ \begin{itemize}
+ \item References different (internal) mapping table for INT or FP
+ \item Actual predicate bitmask ALWAYS from the INT regfile
+ \end{itemize}
+
+\end{frame}
+
+
\frame{\frametitle{Register key-value CSR store}
\begin{itemize}
}
+\begin{frame}[fragile]
+\frametitle{Register key-value CSR table decoding pseudocode}
+
+\begin{semiverbatim}
+struct vectorised fp\_vec[32];
+struct vectorised int\_vec[32];
+
+for (i = 0; i < 16; i++) // 16 CSRs?
+ tb = int\_vec if CSRvectortb[i].type == 0 else fp\_vec
+ idx = CSRvectortb[i].regidx
+ tb[idx].elwidth = CSRpred[i].elwidth
+ tb[idx].regidx = CSRpred[i].regidx
+ tb[idx].isvector = true
+\end{semiverbatim}
+
+ \begin{itemize}
+ \item All 64 (int and FP) Entries zero'd before setting
+ \item Might be a bit complex to set up (TBD)
+ \end{itemize}
+
+\end{frame}
+
+
+\begin{frame}[fragile]
+\frametitle{ADD pseudocode with redirection, this time}
+
+\begin{semiverbatim}
+function op\_add(rd, rs1, rs2, predr) # add not VADD!
+ int i, id=0, irs1=0, irs2=0;
+ rd = int\_vec[rd ].isvector ? int\_vec[rd ].regidx : rd;
+ rs1 = int\_vec[rs1].isvector ? int\_vec[rs1].regidx : rs1;
+ rs2 = int\_vec[rs2].isvector ? int\_vec[rs2].regidx : rs2;
+ predval = get\_pred\_val(FALSE, rd);
+ for (i = 0; i < VL; i++)
+ if (predval \& 1<<i) # predication uses intregs
+ ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
+ if (int\_vec[rd ].isvector) \{ id += 1; \}
+ if (int\_vec[rs1].isvector) \{ irs1 += 1; \}
+ if (int\_vec[rs2].isvector) \{ irs2 += 1; \}
+\end{semiverbatim}
+
+ \begin{itemize}
+ \item SIMD (elwidth != default) not covered above
+ \end{itemize}
+\end{frame}
+
+
\frame{\frametitle{C.MV extremely flexible!}
\begin{itemize}
\frame{\frametitle{What's the downside(s) of SV?}
\begin{itemize}
\item EVERY register operation is inherently parallelised\\
- (scalar ops are just vectors of length 1)\vspace{8pt}
+ (scalar ops are just vectors of length 1)\vspace{4pt}
\item An extra pipeline phase is pretty much essential\\
- for fast low-latency implementations\vspace{8pt}
+ for fast low-latency implementations\vspace{4pt}
\item Assuming an instruction FIFO, N ops could be taken off\\
of a parallel op per cycle (avoids filling entire FIFO;\\
- also is less work per cycle: lower complexity / latency)\vspace{8pt}
+ also is less work per cycle: lower complexity / latency)\vspace{4pt}
\item With zeroing off, skipping non-predicated elements is hard:\\
- it is however an optimisation (and could be skipped).
+ it is however an optimisation (and could be skipped).\vspace{4pt}
+ \item Setting up the Register/Predication tables (interpreting the\\
+ CSR key-value stores) might be a bit complex to optimise
+ (any change to a CSR key-value entry needs to redo the table)
\end{itemize}
}
projects / libreriscv.git / blobdiff