of pipeline setup, amount of state to context switch
and software portability\vspace{4pt}
\item How?
- By implicitly marking INT/FP regs as "Vectorised",\\
+ By marking INT/FP regs as "Vectorised" and
+ adding a level of indirection,
SV expresses how existing instructions should act
on [contiguous] blocks of registers, in parallel.\vspace{4pt}
\item What?
\frame{\frametitle{How is Parallelism abstracted in Simple-V?}
\begin{itemize}
- \item Register "typing" turns any op into an implicit Vector op\vspace{10pt}
+ \item Register "typing" turns any op into an implicit Vector op:\\
+ registers are reinterpreted through a level of indirection
\item Primarily at the Instruction issue phase (except SIMD)\\
Note: it's ok to pass predication through to ALU (like SIMD)
\item Standard (and future, and custom) opcodes now parallel\vspace{10pt}
\item Predication in INT regs as a BIT field (max VL=XLEN)
\item Minimum VL must be Num Regs - 1 (all regs single LD/ST)
\item SV may condense sparse Vecs: RVV lets ALU do predication
- \item NO ZEROING: non-predicated elements are skipped
+ \item Choice to Zero or skip non-predicated elements
\end{itemize}
}
\begin{itemize}
\item Same register(s) can have multiple "interpretations"
+ \item Set "real" register (scalar) without needing to set/unset CSRs.
\item xBitManip plus SIMD plus xBitManip = Hi/Lo bitops
\item (32-bit GREV plus 4x8-bit SIMD plus 32-bit GREV:\\
GREV @ VL=N,wid=32; SIMD @ VL=Nx4,wid=8)
(BEXT/BDEP @ VL=N,wid=32; SIMD @ VL=Nx4,wid=8)
\item Same register(s) can be offset (no need for VSLIDE)\vspace{6pt}
\end{itemize}
- Note:\vspace{10pt}
+ Note:
\begin{itemize}
\item xBitManip reduces O($N^{6}$) SIMD down to O($N^{3}$)
\item Hi-Performance: Macro-op fusion (more pipeline stages?)
Considerations:
\begin{itemize}
\item Complex not really impacted, simple impacted a LOT\\
- with Zeroing... however it's useful (memset)
+ with Zeroing... however it's useful (memzero)
\item Non-zero'd overlapping "Vectors" may issue overlapping ops\\
(2nd op's predicated elements slot in 1st's non-predicated ops)
\item Please don't use Vectors for "security" (use Sec-Ext)
}
+\begin{frame}[fragile]
+\frametitle{Predication key-value CSR table decoding pseudocode}
+
+\begin{semiverbatim}
+struct pred fp_pred[32];
+struct pred int_pred[32];
+
+for (i = 0; i < 16; i++) // 16 CSRs?
+ tb = int\_pred if CSRpred[i].type == 0 else fp\_pred
+ idx = CSRpred[i].regidx
+ tb[idx].zero = CSRpred[i].zero
+ tb[idx].inv = CSRpred[i].inv
+ tb[idx].predidx = CSRpred[i].predidx
+ tb[idx].enabled = true
+\end{semiverbatim}
+
+ \begin{itemize}
+ \item All 64 (int and FP) Entries zero'd before setting
+ \item Might be a bit complex to set up (TBD)
+ \end{itemize}
+
+\end{frame}
+
+
\frame{\frametitle{Register key-value CSR store}
\begin{itemize}
}
+\frame{\frametitle{Register key-value CSR pseudocode}
+
+ \begin{itemize}
+ \item TODO
+ \end{itemize}
+}
+
+
\frame{\frametitle{C.MV extremely flexible!}
\begin{itemize}
\frame{\frametitle{What's the downside(s) of SV?}
\begin{itemize}
\item EVERY register operation is inherently parallelised\\
- (scalar ops are just vectors of length 1)\vspace{8pt}
+ (scalar ops are just vectors of length 1)\vspace{4pt}
\item An extra pipeline phase is pretty much essential\\
- for fast low-latency implementations\vspace{8pt}
+ for fast low-latency implementations\vspace{4pt}
\item Assuming an instruction FIFO, N ops could be taken off\\
of a parallel op per cycle (avoids filling entire FIFO;\\
- also is less work per cycle: lower complexity / latency)\vspace{8pt}
+ also is less work per cycle: lower complexity / latency)\vspace{4pt}
\item With zeroing off, skipping non-predicated elements is hard:\\
- it is however an optimisation (and could be skipped).
+ it is however an optimisation (and could be skipped).\vspace{4pt}
+ \item Setting up the Register/Predication tables (interpreting the\\
+ CSR key-value stores) might be a bit complex to optimise.
\end{itemize}
}
projects / libreriscv.git / blobdiff