\vspace{32pt}
\Large{Flexible Vectorisation}\\
\Large{(aka not so Simple-V?)}\\
+ \Large{(aka How to Parallelise the RISC-V ISA)}\\
\vspace{24pt}
\Large{[proposed for] Chennai 9th RISC-V Workshop}\\
- \vspace{24pt}
+ \vspace{16pt}
\large{\today}
\end{center}
}
\frame{\frametitle{Quick refresher on SIMD}
\begin{itemize}
- \item SIMD very easy to implement (and very seductive)\vspace{10pt}
- \item Parallelism is in the ALU\vspace{10pt}
- \item Zero-to-Negligeable impact for rest of core\vspace{10pt}
+ \item SIMD very easy to implement (and very seductive)\vspace{8pt}
+ \item Parallelism is in the ALU\vspace{8pt}
+ \item Zero-to-Negligeable impact for rest of core\vspace{8pt}
\end{itemize}
Where SIMD Goes Wrong:\vspace{10pt}
\begin{itemize}
\item See "SIMD instructions considered harmful"
- https://www.sigarch.org/simd-instructions-considered-harmful
- \item Corner-cases alone are extremely complex.\\
+ https://sigarch.org/simd-instructions-considered-harmful
+ \item Setup and corner-cases alone are extremely complex.\\
Hardware is easy, but software is hell.
\item O($N^{6}$) ISA opcode proliferation!\\
opcode, elwidth, veclen, src1-src2-dest hi/lo
\begin{itemize}
\item Extremely powerful (extensible to 256 registers)\vspace{10pt}
\item Supports polymorphism, several datatypes (inc. FP16)\vspace{10pt}
- \item Requires a separate Register File (32 w/ext to 256)\vspace{10pt}
+ \item Requires a separate Register File (16 w/ext to 256)\vspace{10pt}
\item Implemented as a separate pipeline (no impact on scalar)\vspace{10pt}
\end{itemize}
However...\vspace{10pt}
\begin{itemize}
\item 98 percent opcode duplication with rest of RV (CLIP)
\item Extending RVV requires customisation not just of h/w:\\
- gcc and s/w also need customisation (and maintenance)
+ gcc, binutils also need customisation (and maintenance)
\end{itemize}
}
of pipeline setup, amount of state to context switch
and software portability\vspace{4pt}
\item How?
- By implicitly marking INT/FP regs as "Vectorised",\\
+ By marking INT/FP regs as "Vectorised" and
+ adding a level of indirection,
SV expresses how existing instructions should act
on [contiguous] blocks of registers, in parallel.\vspace{4pt}
\item What?
Simple-V is an "API" that implicitly extends
- existing (scalar) instructions with explicit parallelisation
+ existing (scalar) instructions with explicit parallelisation\\
(i.e. SV is actually about parallelism NOT vectors per se)
\end{itemize}
}
\frame{\frametitle{What's the value of SV? Why adopt it even in non-V?}
\begin{itemize}
- \item memcpy becomes much smaller (higher bang-per-buck)\vspace{10pt}
- \item context-switch (LOAD/STORE multiple): 1-2 instructions\vspace{10pt}
- \item Compressed instrs further reduces I-cache (etc.)\vspace{10pt}
- \item greatly-reduced I-cache load (and less reads)\vspace{10pt}
- \end{itemize}
- Note:\vspace{10pt}
+ \item memcpy becomes much smaller (higher bang-per-buck)
+ \item context-switch (LOAD/STORE multiple): 1-2 instructions
+ \item Compressed instrs further reduces I-cache (etc.)
+ \item Greatly-reduced I-cache load (and less reads)
+ \item Amazingly, SIMD becomes (more) tolerable\\
+ (corner-cases for setup and teardown are gone)
+ \end{itemize}
+ Note:
\begin{itemize}
\item It's not just about Vectors: it's about instruction effectiveness
+ \item Anything that makes SIMD tolerable has to be a good thing
\item Anything implementor is not interested in HW-optimising,\\
let it fall through to exceptions (implement as a trap).
\end{itemize}
\begin{itemize}
\item A full supercomputer-level Vector Proposal
\item A replacement for RVV (SV is designed to be over-ridden\\
- by - or augmented to become, or just be replaced by - RVV)
+ by - or augmented to become - RVV)
\end{itemize}
}
\frame{\frametitle{How is Parallelism abstracted in Simple-V?}
\begin{itemize}
- \item Register "typing" turns any op into an implicit Vector op\vspace{10pt}
+ \item Register "typing" turns any op into an implicit Vector op:\\
+ registers are reinterpreted through a level of indirection
\item Primarily at the Instruction issue phase (except SIMD)\\
Note: it's ok to pass predication through to ALU (like SIMD)
\item Standard (and future, and custom) opcodes now parallel\vspace{10pt}
\end{itemize}
- Notes:\vspace{6pt}
+ Note: EVERYTHING is parallelised:
\begin{itemize}
\item All LOAD/STORE (inc. Compressed, Int/FP versions)
\item All ALU ops (soft / hybrid / full HW, on per-op basis)
- \item All branches become predication targets (C.FNE added)
+ \item All branches become predication targets (C.FNE added?)
\item C.MV of particular interest (s/v, v/v, v/s)
+ \item FCVT, FMV, FSGNJ etc. very similar to C.MV
\end{itemize}
}
% but MODIFYING the remaining "vectorised" op, subtracting the now
% scalar ops from it.
-\frame{\frametitle{Predicated 8-parallel ADD: optimised (not masked)}
+\frame{\frametitle{Predicated 8-parallel ADD: 1-wide ALU}
+ \begin{center}
+ \includegraphics[height=2.5in]{padd9_alu1.png}\\
+ {\bf \red Predicated adds are shuffled down: 6 cycles in total}
+ \end{center}
+}
+
+
+\frame{\frametitle{Predicated 8-parallel ADD: 4-wide ALU}
\begin{center}
\includegraphics[height=2.5in]{padd9_alu4.png}\\
{\bf \red Predicated adds are shuffled down: 4 in 1st cycle, 2 in 2nd}
\frame{\frametitle{How are SIMD Instructions Vectorised?}
\begin{itemize}
- \item SIMD ALU(s) primarily unchanged\vspace{10pt}
- \item Predication is added to each SIMD element (NO ZEROING!)\vspace{10pt}
- \item End of Vector enables predication (NO ZEROING!)\vspace{10pt}
+ \item SIMD ALU(s) primarily unchanged\vspace{6pt}
+ \item Predication is added to each SIMD element\vspace{6pt}
+ \item Predication bits sent in groups to the ALU\vspace{6pt}
+ \item End of Vector enables (additional) predication\vspace{10pt}
\end{itemize}
- Considerations:\vspace{10pt}
+ Considerations:\vspace{4pt}
\begin{itemize}
- \item Many SIMD ALUs possible (parallel execution)\vspace{10pt}
- \item Very long SIMD ALUs could waste die area (short vectors)\vspace{10pt}
- \item Implementor free to choose (API remains the same)\vspace{10pt}
+ \item Many SIMD ALUs possible (parallel execution)
+ \item Implementor free to choose (API remains the same)
+ \item Unused ALU units wasted, but s/w DRASTICALLY simpler
+ \item Very long SIMD ALUs could waste significant die area
\end{itemize}
}
% With multiple SIMD ALUs at for example 32-bit wide they can be used
\frame{\frametitle{What's the deal / juice / score?}
\begin{itemize}
- \item Standard Register File(s) overloaded with CSR "vector span"\\
+ \item Standard Register File(s) overloaded with CSR "reg is vector"\\
(see pseudocode slides for examples)
- \item Element width and type concepts remain same as RVV\\
+ \item Element width (and type?) concepts remain same as RVV\\
(CSRs are used to "interpret" elements in registers)
\item CSRs are key-value tables (overlaps allowed)\vspace{10pt}
\end{itemize}
\item Predication in INT regs as a BIT field (max VL=XLEN)
\item Minimum VL must be Num Regs - 1 (all regs single LD/ST)
\item SV may condense sparse Vecs: RVV lets ALU do predication
- \item NO ZEROING: non-predicated elements are skipped
+ \item Choice to Zero or skip non-predicated elements
\end{itemize}
}
\frametitle{ADD pseudocode (or trap, or actual hardware loop)}
\begin{semiverbatim}
-function op_add(rd, rs1, rs2, predr) # add not VADD!
+function op\_add(rd, rs1, rs2, predr) # add not VADD!
int i, id=0, irs1=0, irs2=0;
for (i = 0; i < VL; i++)
if (ireg[predr] & 1<<i) # predication uses intregs
ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
- if (reg_is_vectorised[rd]) \{ id += 1; \}
- if (reg_is_vectorised[rs1]) \{ irs1 += 1; \}
- if (reg_is_vectorised[rs2]) \{ irs2 += 1; \}
+ if (reg\_is\_vectorised[rd]) \{ id += 1; \}
+ if (reg\_is\_vectorised[rs1]) \{ irs1 += 1; \}
+ if (reg\_is\_vectorised[rs2]) \{ irs2 += 1; \}
\end{semiverbatim}
\begin{itemize}
+ \item Above is oversimplified: Reg. indirection left out (for clarity).
\item SIMD slightly more complex (case above is elwidth = default)
\item Scalar-scalar and scalar-vector and vector-vector now all in one
\item OoO may choose to push ADDs into instr. queue (v. busy!)
\frametitle{Predication-Branch (or trap, or actual hardware loop)}
\begin{semiverbatim}
-s1 = reg_is_vectorised(src1);
-s2 = reg_is_vectorised(src2);
+s1 = reg\_is\_vectorised(src1);
+s2 = reg\_is\_vectorised(src2);
if (!s2 && !s1) goto branch;
for (int i = 0; i < VL; ++i)
if cmp(s1 ? reg[src1+i] : reg[src1],
if (unit-strided) stride = elsize;
else stride = areg[as2]; // constant-strided
for (int i = 0; i < VL; ++i)
- if (preg_enabled[rd] && ([!]preg[rd] & 1<<i))
+ if (preg\_enabled[rd] && ([!]preg[rd] & 1<<i))
for (int j = 0; j < seglen+1; j++)
- if (reg_is_vectorised[rs2]) offs = vreg[rs2][i]
+ if (reg\_is\_vectorised[rs2]) offs = vreg[rs2+i]
else offs = i*(seglen+1)*stride;
vreg[rd+j][i] = mem[sreg[base] + offs + j*stride]
\end{semiverbatim}
\frame{\frametitle{Why are overlaps allowed in Regfiles?}
\begin{itemize}
- \item Same register(s) can have multiple "interpretations"\vspace{6pt}
- \item xBitManip plus SIMD plus xBitManip = Hi/Lo bitops\vspace{6pt}
- \item (32-bit GREV plus 4x8-bit SIMD plus 32-bit GREV)\vspace{6pt}
- \item RGB 565 (video): BEXTW plus 4x8-bit SIMD plus BDEPW\vspace{6pt}
+ \item Same register(s) can have multiple "interpretations"
+ \item Set "real" register (scalar) without needing to set/unset CSRs.
+ \item xBitManip plus SIMD plus xBitManip = Hi/Lo bitops
+ \item (32-bit GREV plus 4x8-bit SIMD plus 32-bit GREV:\\
+ GREV @ VL=N,wid=32; SIMD @ VL=Nx4,wid=8)
+ \item RGB 565 (video): BEXTW plus 4x8-bit SIMD plus BDEPW\\
+ (BEXT/BDEP @ VL=N,wid=32; SIMD @ VL=Nx4,wid=8)
\item Same register(s) can be offset (no need for VSLIDE)\vspace{6pt}
\end{itemize}
- Note:\vspace{10pt}
+ Note:
\begin{itemize}
\item xBitManip reduces O($N^{6}$) SIMD down to O($N^{3}$)
\item Hi-Performance: Macro-op fusion (more pipeline stages?)
}
-\frame{\frametitle{Why no Zeroing (place zeros in non-predicated elements)?}
+\frame{\frametitle{To Zero or not to place zeros in non-predicated elements?}
\begin{itemize}
- \item Zeroing is an implementation optimisation favouring OoO\vspace{8pt}
- \item Simple implementations may skip non-predicated operations\vspace{8pt}
- \item Simple implementations explicitly have to destroy data\vspace{8pt}
+ \item Zeroing is an implementation optimisation favouring OoO
+ \item Simple implementations may skip non-predicated operations
+ \item Simple implementations explicitly have to destroy data
\item Complex implementations may use reg-renames to save power\\
Zeroing on predication chains makes optimisation harder
+ \item Compromise: REQUIRE both (specified in predication CSRs).
\end{itemize}
- Considerations:\vspace{10pt}
+ Considerations:
\begin{itemize}
- \item Complex not really impacted, Simple impacted a LOT
- \item Overlapping "Vectors" may issue overlapping ops
+ \item Complex not really impacted, simple impacted a LOT\\
+ with Zeroing... however it's useful (memzero)
+ \item Non-zero'd overlapping "Vectors" may issue overlapping ops\\
+ (2nd op's predicated elements slot in 1st's non-predicated ops)
\item Please don't use Vectors for "security" (use Sec-Ext)
\end{itemize}
}
\item key is int regfile number or FP regfile number (1 bit)\vspace{6pt}
\item register to be predicated if referred to (5 bits, key)\vspace{6pt}
\item register to store actual predication in (5 bits, value)\vspace{6pt}
- \item predication is inverted (1 bit)\vspace{6pt}
- \item non-predicated elements are to be zero'd (1 bit)\vspace{6pt}
+ \item predication is inverted Y/N (1 bit)\vspace{6pt}
+ \item non-predicated elements are to be zero'd Y/N (1 bit)\vspace{6pt}
\end{itemize}
Notes:\vspace{10pt}
\begin{itemize}
}
+\begin{frame}[fragile]
+\frametitle{Predication key-value CSR table decoding pseudocode}
+
+\begin{semiverbatim}
+struct pred fp\_pred[32];
+struct pred int\_pred[32];
+
+for (i = 0; i < 16; i++) // 16 CSRs?
+ tb = int\_pred if CSRpred[i].type == 0 else fp\_pred
+ idx = CSRpred[i].regidx
+ tb[idx].zero = CSRpred[i].zero
+ tb[idx].inv = CSRpred[i].inv
+ tb[idx].predidx = CSRpred[i].predidx
+ tb[idx].enabled = true
+\end{semiverbatim}
+
+ \begin{itemize}
+ \item All 64 (int and FP) Entries zero'd before setting
+ \item Might be a bit complex to set up (TBD)
+ \end{itemize}
+
+\end{frame}
+
+
+\begin{frame}[fragile]
+\frametitle{Get Predication value pseudocode}
+
+\begin{semiverbatim}
+def get\_pred\_val(bool is\_fp\_op, int reg):
+ tb = int\_pred if is\_fp\_op else fp\_pred
+ if (!tb[reg].enabled):
+ return ~0x0 // all ops enabled
+ predidx = tb[reg].predidx // redirection occurs HERE
+ predicate = intreg[predidx] // actual predicate HERE
+ if (tb[reg].inv):
+ predicate = ~predicate
+ return predicate
+\end{semiverbatim}
+
+ \begin{itemize}
+ \item References different (internal) mapping table for INT or FP
+ \item Actual predicate bitmask ALWAYS from the INT regfile
+ \end{itemize}
+
+\end{frame}
+
+
\frame{\frametitle{Register key-value CSR store}
\begin{itemize}
}
+\begin{frame}[fragile]
+\frametitle{Register key-value CSR table decoding pseudocode}
+
+\begin{semiverbatim}
+struct vectorised fp\_vec[32];
+struct vectorised int\_vec[32];
+
+for (i = 0; i < 16; i++) // 16 CSRs?
+ tb = int\_vec if CSRvectortb[i].type == 0 else fp\_vec
+ idx = CSRvectortb[i].regidx
+ tb[idx].elwidth = CSRpred[i].elwidth
+ tb[idx].regidx = CSRpred[i].regidx
+ tb[idx].isvector = true
+\end{semiverbatim}
+
+ \begin{itemize}
+ \item All 64 (int and FP) Entries zero'd before setting
+ \item Might be a bit complex to set up (TBD)
+ \end{itemize}
+
+\end{frame}
+
+
+\begin{frame}[fragile]
+\frametitle{ADD pseudocode with redirection, this time}
+
+\begin{semiverbatim}
+function op\_add(rd, rs1, rs2) # add not VADD!
+ int i, id=0, irs1=0, irs2=0;
+ rd = int\_vec[rd ].isvector ? int\_vec[rd ].regidx : rd;
+ rs1 = int\_vec[rs1].isvector ? int\_vec[rs1].regidx : rs1;
+ rs2 = int\_vec[rs2].isvector ? int\_vec[rs2].regidx : rs2;
+ predval = get\_pred\_val(FALSE, rd);
+ for (i = 0; i < VL; i++)
+ if (predval \& 1<<i) # predication uses intregs
+ ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
+ if (int\_vec[rd ].isvector) \{ id += 1; \}
+ if (int\_vec[rs1].isvector) \{ irs1 += 1; \}
+ if (int\_vec[rs2].isvector) \{ irs2 += 1; \}
+\end{semiverbatim}
+
+ \begin{itemize}
+ \item SIMD (elwidth != default) not covered above
+ \end{itemize}
+\end{frame}
+
+
\frame{\frametitle{C.MV extremely flexible!}
\begin{itemize}
- \item scalar-to-vector (w/no pred): VSPLAT
- \item scalar-to-vector (w/dest-pred): Sparse VSPLAT
- \item scalar-to-vector (w/single dest-pred): VINSERT
- \item vector-to-scalar (w/src-pred): VEXTRACT
- \item vector-to-vector (w/no pred): Vector Copy
- \item vector-to-vector (w/src xor dest pred): Sparse Vector Copy
- \item vector-to-vector (w/src and dest pred): Vector Gather/Scatter
- \end{itemize}
- \vspace{8pt}
- Notes:\vspace{10pt}
+ \item scalar-to-vector (w/ no pred): VSPLAT
+ \item scalar-to-vector (w/ dest-pred): Sparse VSPLAT
+ \item scalar-to-vector (w/ 1-bit dest-pred): VINSERT
+ \item vector-to-scalar (w/ [1-bit?] src-pred): VEXTRACT
+ \item vector-to-vector (w/ no pred): Vector Copy
+ \item vector-to-vector (w/ src pred): Vector Gather
+ \item vector-to-vector (w/ dest pred): Vector Scatter
+ \item vector-to-vector (w/ src \& dest pred): Vector Gather/Scatter
+ \end{itemize}
+ \vspace{4pt}
+ Notes:
\begin{itemize}
- \item Really powerful!
- \item Any other options?
+ \item Surprisingly powerful!
+ \item Same arrangement for FVCT, FMV, FSGNJ etc.
\end{itemize}
}
+\begin{frame}[fragile]
+\frametitle{MV pseudocode with predication}
+
+\begin{semiverbatim}
+function op\_mv(rd, rs) # MV not VMV!
+ rd = int\_vec[rd].isvector ? int\_vec[rd].regidx : rd;
+ rs = int\_vec[rs].isvector ? int\_vec[rs].regidx : rs;
+ ps = get\_pred\_val(FALSE, rs); # predication on src
+ pd = get\_pred\_val(FALSE, rd); # ... AND on dest
+ for (int i = 0, int j = 0; i < VL && j < VL;):
+ if (int\_vec[rs].isvec) while (!(ps \& 1<<i)) i++;
+ if (int\_vec[rd].isvec) while (!(pd \& 1<<j)) j++;
+ ireg[rd+j] <= ireg[rs+i];
+ if (int\_vec[rs].isvec) i++;
+ if (int\_vec[rd].isvec) j++;
+\end{semiverbatim}
+
+ \begin{itemize}
+ \item elwidth != default not covered above (might be a bit hairy)
+ \item Ending early with 1-bit predication not included (VINSERT)
+ \end{itemize}
+\end{frame}
+
+
\frame{\frametitle{Opcodes, compared to RVV}
\begin{itemize}
}
+\begin{frame}[fragile]
+\frametitle{Example c code: DAXPY}
+
+\begin{semiverbatim}
+ void daxpy(size_t n, double a,
+ const double x[], double y[])
+ \{
+ for (size_t i = 0; i < n; i++) \{
+ y[i] = a*x[i] + y[i];
+ \}
+ \}
+\end{semiverbatim}
+
+ \begin{itemize}
+ \item See "SIMD Considered Harmful" for SIMD/RVV analysis\\
+ https://sigarch.org/simd-instructions-considered-harmful/
+ \end{itemize}
+
+
+\end{frame}
+
+
+\begin{frame}[fragile]
+\frametitle{RVV DAXPY assembly (RV32V)}
+
+\begin{semiverbatim}
+# a0 is n, a1 is ptr to x[0], a2 is ptr to y[0], fa0 is a
+ li t0, 2<<25
+ vsetdcfg t0 # enable 2 64b Fl.Pt. registers
+loop:
+ setvl t0, a0 # vl = t0 = min(mvl, n)
+ vld v0, a1 # load vector x
+ slli t1, t0, 3 # t1 = vl * 8 (in bytes)
+ vld v1, a2 # load vector y
+ add a1, a1, t1 # increment pointer to x by vl*8
+ vfmadd v1, v0, fa0, v1 # v1 += v0 * fa0 (y = a * x + y)
+ sub a0, a0, t0 # n -= vl (t0)
+ vst v1, a2 # store Y
+ add a2, a2, t1 # increment pointer to y by vl*8
+ bnez a0, loop # repeat if n != 0
+\end{semiverbatim}
+\end{frame}
+
+
+\begin{frame}[fragile]
+\frametitle{SV DAXPY assembly (RV64G)}
+
+\begin{semiverbatim}
+# a0 is n, a1 is ptr to x[0], a2 is ptr to y[0], fa0 is a
+ CSRvect1 = \{type: F, key: a3, val: a3, elwidth: dflt\}
+ CSRvect2 = \{type: F, key: a7, val: a7, elwidth: dflt\}
+loop:
+ setvl t0, a0, 4 # vl = t0 = min(4, n)
+ ld a3, a1 # load 4 registers a3-6 from x
+ slli t1, t0, 3 # t1 = vl * 8 (in bytes)
+ ld a7, a2 # load 4 registers a7-10 from y
+ add a1, a1, t1 # increment pointer to x by vl*8
+ fmadd a7, a3, fa0, a7 # v1 += v0 * fa0 (y = a * x + y)
+ sub a0, a0, t0 # n -= vl (t0)
+ st a7, a2 # store 4 registers a7-10 to y
+ add a2, a2, t1 # increment pointer to y by vl*8
+ bnez a0, loop # repeat if n != 0
+\end{semiverbatim}
+\end{frame}
+
+
\frame{\frametitle{Under consideration}
\begin{itemize}
\item Can VSELECT be removed? (it's really complex)
\item Can CLIP be done as a CSR (mode, like elwidth)
\item SIMD saturation (etc.) also set as a mode?
- \item C.MV src predication no different from dest predication\\
- What to do? Make one have different meaning?
\item 8/16-bit ops is it worthwhile adding a "start offset"? \\
(a bit like misaligned addressing... for registers)\\
or just use predication to skip start?
\frame{\frametitle{What's the downside(s) of SV?}
\begin{itemize}
\item EVERY register operation is inherently parallelised\\
- (scalar ops are just vectors of length 1)
+ (scalar ops are just vectors of length 1)\vspace{4pt}
\item An extra pipeline phase is pretty much essential\\
- for fast low-latency implementations
+ for fast low-latency implementations\vspace{4pt}
\item Assuming an instruction FIFO, N ops could be taken off\\
of a parallel op per cycle (avoids filling entire FIFO;\\
- also is less work per cycle: lower complexity / latency)
+ also is less work per cycle: lower complexity / latency)\vspace{4pt}
\item With zeroing off, skipping non-predicated elements is hard:\\
- it is however an optimisation (and could be skipped).
+ it is however an optimisation (and could be skipped).\vspace{4pt}
+ \item Setting up the Register/Predication tables (interpreting the\\
+ CSR key-value stores) might be a bit complex to optimise
+ (any change to a CSR key-value entry needs to redo the table)
\end{itemize}
}
}
-\frame{\frametitle{TODO (break into separate slides)}
-
- \begin{itemize}
- \item Then explain why this proposal is a good way to \\
- abstract parallelism\\
- (hopefully also explaining how \\
- a good compiler can make clever use of this increase parallelism\\
- Then explain how this can be implemented (at instruction\\
- issue time???) with\\
- implementation options, and what these "cost".\\
- Finally give examples that show simple usage that compares\\
- C code\\
- RVIC\\
- RVV\\
- RVICXsimplev
- \end{itemize}
-}
-
-
\frame{\frametitle{Summary}
\begin{itemize}
- \item Designed for flexibility (graded levels of complexity)\vspace{6pt}
- \item Huge range of implementor freedom\vspace{6pt}
- \item Fits RISC-V ethos: achieve more with less\vspace{6pt}
+ \item Actually about parallelism, not Vectors (or SIMD) per se
+ \item Only needs 3 actual instructions (plus CSRs)\\
+ RVV - and "standard" SIMD - require ISA duplication
+ \item Designed for flexibility (graded levels of complexity)
+ \item Huge range of implementor freedom
+ \item Fits RISC-V ethos: achieve more with less
\item Reduces SIMD ISA proliferation by 3-4 orders of magnitude \\
- (without SIMD downsides or sacrificing speed trade-off)\vspace{6pt}
- \item Covers 98\% of RVV, allows RVV to fit "on top"\vspace{6pt}
+ (without SIMD downsides or sacrificing speed trade-off)
+ \item Covers 98\% of RVV, allows RVV to fit "on top"
\item Not designed for supercomputing (that's RVV), designed for
- in between: DSPs, RV32E, Embedded 3D GPUs etc.\vspace{6pt}
+ in between: DSPs, RV32E, Embedded 3D GPUs etc.
\item Not specifically designed for Vectorisation: designed to\\
reduce code size (increase efficiency, just
- like Compressed)\vspace{6pt}
- \end{itemize}
-}
-
-
-\frame{\frametitle{slide}
-
- \begin{itemize}
- \item \vspace{10pt}
- \end{itemize}
- Considerations:\vspace{10pt}
- \begin{itemize}
- \item \vspace{10pt}
+ like Compressed)
\end{itemize}
}
projects / libreriscv.git / blobdiff