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[libreriscv.git] / simple_v_extension / specification / sv.setvl.mdwn

diff --git a/simple_v_extension/specification/sv.setvl.mdwn b/simple_v_extension/specification/sv.setvl.mdwn
index c32623bffd569e66776e0076f8c0bd1cd20ffa66..a7eea7a9888188364e99fc401a55a7f816e4f94b 100644 (file)
--- a/simple_v_extension/specification/sv.setvl.mdwn
+++ b/simple_v_extension/specification/sv.setvl.mdwn
@@ -1,51 +1,54 @@
-# SV setvl exploration
-
-Formats for Vector Configuration Instructions under OP-V major opcode:
-                                                             
-| 31|30         25|24      20|19      15|14   12|11      7|6     0| name    |
-|---|------------------------|----------|-------|---------|-------|---------|
-| 0 | zimm[10:6]  |imm[4:0]  |    rs1   | 1 1 1 |    rd   |1010111| vsetvli |
-| 1 |   000000    |   rs2    |    rs1   | 1 1 1 |    rd   |1010111| vsetvl  |
-| 1 |      6      |     5    |     5    |   3   |    5    |   7   |         |
-
-Requirement: fit MVL into this format.
-                                                             
-| 31|30         25|24      20|19      15|14   12|11      7|6     0| name    |
-|---|-------------|----------|----------|-------|---------|-------|---------|
-| 0 | zimm[10:6]  |imm[4:0]  |    rs1   | 1 1 1 |    rd   |1010111| vsetvli |
-| 1 |   imm[5:0]  |   rs2    |    rs1   | 1 1 1 |    rd   |1010111| vsetvl  |
-| 1 |      6      |     5    |     5    |   3   |    5    |   7   |         |
-
-where:
-* when bit 31==0, both MVL and VL are set to imm(5:0) - plus one to
-  get it out of the "NOP" scenario.
-* when bit 31==1, MVL is set to imm(5:0) plus one.
-
-hang on... no, that's a 4-argument setvl!  what about this?
-
-
-| 31            25|24      20|19      15|14   12|11      7|6     0| name    | variant# - |
-|-----------------|----------|----------|-------|---------|-------|---------|------------|
-| 0 | imm[5:0]    | 0b00000  |    rs1   | 1 1 1 |    rd   |1010111| vsetvli | 1          |
-| 0 | imm[5:0]    | 0b00000  |  0b00000 | 1 1 1 |    rd   |1010111| vsetvli | 2          |
-| 0 |   imm[5:0]  | rs2!=x0  |    rs1   | 1 1 1 |    rd   |1010111| vsetvli | 3          |
-| 0 |   imm[5:0]  | rs2!=x0  |  0b00000 | 1 1 1 |    rd   |1010111| vsetvli | 4          |
-| 1 | imm[5:0]    | 0b00000  |    rs1   | 1 1 1 |    rd   |1010111| vsetvl  | 5          |
-| 1 | imm[5:0]    | 0b00000  |  0b00000 | 1 1 1 |    rd   |1010111| vsetvl  | 6          |
-| 1 |   imm[5:0]  | rs2!=x0  |    rs1   | 1 1 1 |    rd   |1010111| vsetvl  | 7          |
-| 1 |   imm[5:0]  | rs2!=x0  |  0b00000 | 1 1 1 |    rd   |1010111| vsetvl  | 8          |
-| 1 |      6      |     5    |     5    |   3   |    5    |   7   |         |            |
-
-i think those are the 8 permutations: what can those be used for?
-
-| name    | variant# - | purpose                                        |
-|---------|------------|------------------------------------------------|
-| vsetvli | 1          | TBD                                            |
-| vsetvli | 2          | TBD                                            |
-| vsetvli | 3          | TBD                                            |
-| vsetvli | 4          | TBD                                            |
-| vsetvl  | 5          | TBD                                            |
-| vsetvl  | 6          | TBD                                            |
-| vsetvl  | 7          | TBD                                            |
-| vsetvl  | 8          | TBD                                            |
+[[!tag standards]]
+
+# SV setvl
+
+sv.setvl allows optional setting of both MVL and of indirectly marking
+one of the scalar registers as being VL.
+
+Unlike the majority of other CSRs, which contain status bits that change
+behaviour, VL is closely interlinked with the instructions it affects
+and often requires arithmetic interaction.  Thus it makes more sense to
+actually *use* one of the scalar registers *as* VL.
+
+Format for Vector Configuration Instructions under OP-V major opcode:
+
+| 31|30...20|19....15|14..12|11.7|6.....0| name       |
+|---|-------|--------|------|----|-------|------------|
+| 0 | VLMAX | rs1    | 111  | rd |1010111| sv.setvl   |
+| 0 | VLMAX | 0 (x0) | 111  | rd |1010111| sv.setvl   |
+| 1 | --    | --     | 111  | -- |1010111| *reserved* |
+
+
+# pseudocode
+
+    regs = [0u64; 128];
+    vlval = 0;
+    vl = rd;
+
+    // instruction fields:
+    rd = get_rd_field();
+    rs1 = get_rs1_field();
+    vlmax = get_immed_field();
+
+    // handle illegal instruction decoding
+    if vlmax > XLEN {
+        trap()
+    }
+
+    // calculate VL
+    if rs1 == 0 { // rs1 is x0
+        vlval = vlmax
+    } else {
+        vlval = min(regs[rs1], vlmax)
+    }
+
+    // write rd
+    if rd != 0 {
+        // rd is not x0
+        regs[rd] = vlval;
+    }
+
+# questions <a name="questions"></>
+
+Moved to [[discussion]]