+RVC
+===
+
+The comment in the RVC section says that the Opcodes will be evaluated
+to see which are most useful to provide.
+
+This takes a huge amount of time and, if not *exactly* RVC, would require
+a special decode engine, taking up extra gates as well as need time
+to develop.
+
+Far better to just embed RVC into the opcode and prefix it. This is
+inline with the strategic principle behind SV: "No new opcodes, only
+prefixed augmentation"
+
+Taking an entire major 32 bit opcode (or two) seems logical (RV128
+space). I type funct3 to specify the C type page, Imm 12 bits for the
+operation.
+
+Or, just "to hell with it" and just take the entire opcode and stuff C
+into it, no regard for R/I/U/S and instead do whatever we like.
+
+
++----------+------+---------------------+---------------------+-------+--------+
+| 15 14 13 | 12 | 11 10 9 8 7 | 6 5 4 3 2 | 1 0 | format |
++----------+------+---------------------+---------------------+-------+--------+
+| funct4 | rd/rs1 | rs2 | op | CR |
++----------+------+---------------------+---------------------+-------+--------+
+|funct3 | imm | rd/rs1 | imm | op | CI |
++----------+------+---------------------+---------------------+-------+--------+
+|funct3 | imm | rs2 | op | CSS |
++----------+----------------------------+---------+-----------+-------+--------+
+|funct3 | imm | rd' | op | CIW |
++----------+----------------+-----------+---------+-----------+-------+--------+
+|funct3 | imm | rs1' | imm | rd' | op | CL |
++----------+----------------+-----------+---------+-----------+-------+--------+
+|funct3 | imm | rs1' | imm | rs2' | op | CS |
++----------+----------------+-----------+---------+-----------+-------+--------+
+| funct6 | rd'/rs1' | funct2 | rs2' | op | CA |
++----------+----------------+-----------+---------+-----------+-------+--------+
+|funct3 | offset | rs1' | offset | op | CB |
++----------+----------------+-----------+---------------------+-------+--------+
+|funct3 | jump target | op | CJ |
++----------+--------------------------------------------------+-------+--------+
+
+* top 14 bits of RVC to go into "MAJOR OPCODE 0-2" to represent
+ RVC op[1:0] == 0b00, 0b01 and 0b02. Therefore,
+ 18 bits remain in the 32-bit opcode space
+* 32-bit opcode prefix takes 7 bits, therefore 11 bits remain to fit
+ a SVPrefix.
+* compared to P48, 11 bits are needed, and we have a match.
+
+P48:
+
++---------------+--------+--------+----------+-----+--------+-------------+------+
+| Encoding | 17 | 16 | 15 | 14 | 13 | 12 | 11:7 |
++---------------+--------+--------+----------+-----+--------+-------------+------+
+| P32C-LD-type | rd[5] | rs1[5] | vitp7[6] | vd | vs1 | vitp7[5:0] |
++---------------+--------+--------+----------+-----+--------+-------------+------+
+| P32C-ST-type |vitp7[6]| rs1[5] | rs2[5] | vs2 | vs1 | vitp7[5:0] |
++---------------+--------+--------+----------+-----+--------+-------------+------+
+| P32C-R-type | rd[5] | rs1[5] | rs2[5] | vs2 | vs1 | vitp6 |
++---------------+--------+--------+----------+-----+--------+--------------------+
+| P32C-I-type | rd[5] | rs1[5] | vitp7[6] | vd | vs1 | vitp7[5:0] |
++---------------+--------+--------+----------+-----+--------+--------------------+
+| P32C-U-type | rd[5] | *Rsvd* | *Rsvd* | vd | *Rsvd* | vitp6 |
++---------------+--------+--------+----------+-----+--------+-------------+------+
+| P32C-FR-type | rd[5] | rs1[5] | rs2[5] | vs2 | vs1 | *Rsvd* | vtp5 |
++---------------+--------+--------+----------+-----+--------+-------------+------+
+| P32C-FI-type | rd[5] | rs1[5] | vitp7[6] | vd | vs1 | vitp7[5:0] |
++---------------+--------+--------+----------+-----+--------+-------------+------+
+| P32C-FR4-type | rd[5] | rs1[5] | rs2[5] | vs2 | rs3[5] | vs3 [#fr4]_ | vtp5 |
++---------------+--------+--------+----------+-----+--------+-------------+------+
+
+P32C Prefix:
+
++---------------+--------+--------+-----+--------+-----+------------+
+| Encoding | 31 | 30 | 29 | 28 | 27 | 26:21 |
++---------------+--------+--------+-----+--------+-----+------------+
+| P32C-CL-type | rd[5] | rs1[5] | vd | vs1 | vitp7[5:0] |
++---------------+--------+--------+-----+--------+------------------+
+| P32C-CS-type | rs2[5] | rs1[5] | vs2 | vs1 | vitp7[5:0] |
++---------------+--------+--------+-----+--------+-----+------------+
+| P32C-CR-type | rd[5] | rs1[5] | vd | vs1 |*Rsv*| vitp6 |
++---------------+--------+--------+-----+--------+-----+------------+
+| P32C-CI1-type | rd[5] | rs1[5] | vd | vs1 | vitp7[5:0] |
++---------------+--------+--------+-----+--------+-----+------------+
+| P32C-CI2-type | rd[5] | *Rsvd* | vd | *Rsvd* |*Rsv*| vitp6 |
++---------------+--------+--------+-----+--------+-----+------------+
+| P32C-CB-type | *Rsvd* | rs1[5] |*Rsv*| vs1 | vitp7[5:0] |
++---------------+--------+--------+-----+--------+------------------+
+| P32C-CMv-type | rd[5] | rs1[5] | vd | vs1 | vitp7[5:0] |
++---------------+--------+--------+-----+--------+------------------+
+
+Mapping P32-* Quadrants 0-2 to CUSTOM OPCODEs 0-2:
+
++-------------+--------+-----------+----------+
+| Encoding | 31:21 | 20:7 | 6:0 |
++-------------+--------+-----------+----------+
+| P32C RVC-Q0 | P32-* | RVC[15:2] | OPCODE-0 |
++-------------+--------+-----------+----------+
+| P32C RVC-Q1 | P32-* | RVC[15:2] | OPCODE-1 |
++-------------+--------+-----------+----------+
+| P32C RVC-Q2 | P32-* | RVC[15:2] | OPCODE-2 |
++-------------+--------+-----------+----------+
+
+Notes:
+
+* Branch type requires 2 predicate registers as the second
+ is used to store the combined results of the comparisons
+ (not as twin-predication). The tpred field is therefore
+ used to determine whether x10 is enabled as the second
+ register. TDB, there may be a better (unique) encoding
+
Questions
=========
experiment 2:
-+-----------+-------------+------------+--------------+------------+-----------------------------------------------+
-| VLtyp[11] | VLtyp[10:6] | VLtyp[5] | VLtyp[4:3] | VLtyp[2:0] | comment |
-+-----------+-------------+------------+--------------+------------+-----------------------------------------------+
-| 0 | 00000 | 0 00 | 000 | no change to VL/MVL |
-+-----------+-------------+---------------------------+------------+-----------------------------------------------+
-| 0 | imm | 000 | rs'!=0 | MVL = imm; vl = min(r[rs'], MVL) |
-+-----------+-------------+---------------------------+------------+-----------------------------------------------+
-| 0 | imm | rd'!=0 | 000 | MVL = imm; vl = MVL; r[rd'] = vl |
-+-----------+-------------+---------------------------+------------+-----------------------------------------------+
-| 0 | imm | rd'!=0 | rs'!=0 | MVL = imm; vl = min(r[rs'], MVL); r[rd'] = vl |
-+-----------+-------------+------------+--------------+------------+-----------------------------------------------+
-| 1 | imm | 0 | 00 000 | MVL = imm; vl = MVL; |
-+-----------+-------------+------------+---------------------------+-----------------------------------------------+
-| 1 | imm | 0 | rd[4:0] | MVL = imm; vl = MVL; r[rd] = vl |
-+-----------+-------------+------------+---------------------------+-----------------------------------------------+
-| 1 | imm | 1 | 00 000 | reserved |
-+-----------+-------------+------------+---------------------------+-----------------------------------------------+
-| 1 | imm | 1 | rs1[4:0] | MVL = imm; vl = min(r[rs], MVL) |
-+-----------+-------------+------------+---------------------------+-----------------------------------------------+
++----+------+-----+-------+----------+-----------------------------------------------+
+| 11 | 10:6 | 5 | 4:3 | 2:0 | comment |
++----+------+-----+-------+----------+-----------------------------------------------+
+| 0 | 000 | 000 | 000 | no change to VL/MVL |
++----+------+-------------+----------+-----------------------------------------------+
+| 0 | imm | 000 | rs'!=0 | MVL = imm; vl = min(r[rs'], MVL) |
++----+------+-------------+----------+-----------------------------------------------+
+| 0 | imm | rd'!=0 | 000 | MVL = imm; vl = MVL; r[rd'] = vl |
++----+------+-------------+----------+-----------------------------------------------+
+| 0 | imm | rd'!=0 | rs'!=0 | MVL = imm; vl = min(r[rs'], MVL); r[rd'] = vl |
++----+------+-----+-------+----------+-----------------------------------------------+
+| 1 | imm | 0 | 00 000 | MVL = imm; vl = MVL; |
++----+------+-----+------------------+-----------------------------------------------+
+| 1 | imm | 0 | rd[4:0] | MVL = imm; vl = MVL; r[rd] = vl |
++----+------+-----+------------------+-----------------------------------------------+
+| 1 | imm | 1 | 00 000 | reserved |
++----+------+-----+------------------+-----------------------------------------------+
+| 1 | imm | 1 | rs1[4:0] | MVL = imm; vl = min(r[rs], MVL) |
++----+------+-----+------------------+-----------------------------------------------+
interestingly, "VLtyp[11] = 0" fits the sv.setvl pseudcode really well.
projects / libreriscv.git / blobdiff