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[libreriscv.git] / simple_v_extension / sv_prefix_proposal / discussion.rst

diff --git a/simple_v_extension/sv_prefix_proposal/discussion.rst b/simple_v_extension/sv_prefix_proposal/discussion.rst
index 5487da51f02ba4f20afd80d21e8dc11654f53c67..cc4438bd585aebf7b2c10eb172f7f685598406fd 100644 (file)
--- a/simple_v_extension/sv_prefix_proposal/discussion.rst
+++ b/simple_v_extension/sv_prefix_proposal/discussion.rst
@@ -1,15 +1,23 @@
 RVC
 ===
 
-The comment in the RVC section says that the Opcodes will be evaluated to see which are most useful to provide.
+The comment in the RVC section says that the Opcodes will be evaluated
+to see which are most useful to provide.
 
-This takes a huge amount of time and, if not *exactly* RVC, would require a special decode engine, taking up extra gates as well as need time to develop.
+This takes a huge amount of time and, if not *exactly* RVC, would require
+a special decode engine, taking up extra gates as well as need time
+to develop.
 
-Far better to just embed RVC into the opcode and prefix it. This is inline with the strategic principle behind SV: "No new opcodes, only prefixed augmentation"
+Far better to just embed RVC into the opcode and prefix it. This is
+inline with the strategic principle behind SV: "No new opcodes, only
+prefixed augmentation"
 
-Taking an entire major 32 bit opcode (or two) seems logical (RV128 space). I type funct3 to specify the C type page, Imm 12 bits for the operation.
+Taking an entire major 32 bit opcode (or two) seems logical (RV128
+space). I type funct3 to specify the C type page, Imm 12 bits for the
+operation.
 
-Or, just "to hell with it" and just take the entire opcode and stuff C into it, no regard for R/I/U/S and instead do whatever we like.
+Or, just "to hell with it" and just take the entire opcode and stuff C
+into it, no regard for R/I/U/S and instead do whatever we like.
 
 
 +----------+------+---------------------+---------------------+-------+--------+
@@ -65,21 +73,23 @@ P48:
 
 P32C Prefix:
 
-+---------------+--------+--------+----------+-----+--------+------------+
-| Encoding      | 31     | 30     | 29       | 28  | 27     | 26:21      |
-+---------------+--------+--------+----------+-----+--------+------------+
-| P32C-CL-type  | rd[5]  | rs1[5] | vitp7[6] | vd  | vs1    | vitp7[5:0] |
-+---------------+--------+--------+----------+-----+--------+------------+
-| P32C-CS-type  | rs2[5] | rs1[5] | vitp7[6] | vs2 | vs1    | vitp7[5:0] |
-+---------------+--------+--------+----------+-----+--------+------------+
-| P32C-CR-type  | rd[5]  | rs1[5] | *Rsvd*   | vd  | vs1    | vitp6      |
-+---------------+--------+--------+----------+-----+--------+------------+
-| P32C-CI1-type | rd[5]  | rs1[5] | vitp7[6] | vd  | vs1    | vitp7[5:0] |
-+---------------+--------+--------+----------+-----+--------+------------+
-| P32C-CI2-type | rd[5]  | *Rsvd* | *Rsvd*   | vd  | *Rsvd* | vitp6      |
-+---------------+--------+--------+----------+-----+--------+------------+
-| P32C-CMv-type | rd[5]  | rs1[5] | vitp7[6] | vd  | vs1    | vitp7[5:0] |
-+---------------+--------+--------+----------+-----+--------+------------+
++---------------+--------+--------+-----+--------+-----+------------+
+| Encoding      | 31     | 30     | 29  | 28     | 27  | 26:21      |
++---------------+--------+--------+-----+--------+-----+------------+
+| P32C-CL-type  | rd[5]  | rs1[5] | vd  | vs1    | vitp7[5:0]       |
++---------------+--------+--------+-----+--------+------------------+
+| P32C-CS-type  | rs2[5] | rs1[5] | vs2 | vs1    | vitp7[5:0]       |
++---------------+--------+--------+-----+--------+-----+------------+
+| P32C-CR-type  | rd[5]  | rs1[5] | vd  | vs1    |*Rsv*| vitp6      |
++---------------+--------+--------+-----+--------+-----+------------+
+| P32C-CI1-type | rd[5]  | rs1[5] | vd  | vs1    | vitp7[5:0]       |
++---------------+--------+--------+-----+--------+-----+------------+
+| P32C-CI2-type | rd[5]  | *Rsvd* | vd  | *Rsvd* |*Rsv*| vitp6      |
++---------------+--------+--------+-----+--------+-----+------------+
+| P32C-CB-type  | *Rsvd* | rs1[5] |*Rsv*| vs1    | vitp7[5:0]       |
++---------------+--------+--------+-----+--------+------------------+
+| P32C-CMv-type | rd[5]  | rs1[5] | vd  | vs1    | vitp7[5:0]       |
++---------------+--------+--------+-----+--------+------------------+
 
 Mapping P32-* Quadrants 0-2 to CUSTOM OPCODEs 0-2:
 
@@ -93,6 +103,14 @@ Mapping P32-* Quadrants 0-2 to CUSTOM OPCODEs 0-2:
 | P32C RVC-Q2 | P32-*  | RVC[15:2] | OPCODE-2 |
 +-------------+--------+-----------+----------+
 
+Notes:
+
+* Branch type requires 2 predicate registers as the second
+  is used to store the combined results of the comparisons
+  (not as twin-predication).  The tpred field is therefore
+  used to determine whether x10 is enabled as the second
+  register.  TDB, there may be a better (unique) encoding
+
 Questions
 =========