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[libreriscv.git] / simple_v_extension / vblock_format / discussion.mdwn

diff --git a/simple_v_extension/vblock_format/discussion.mdwn b/simple_v_extension/vblock_format/discussion.mdwn
index 6ad14d4a81d235df9ff9b3eb2bc15dc4bd635196..baee7edf2a1b05ba7de5dc850edd9abb25ce640a 100644 (file)
--- a/simple_v_extension/vblock_format/discussion.mdwn
+++ b/simple_v_extension/vblock_format/discussion.mdwn
@@ -4,7 +4,7 @@ This VBLOCK mode effectively extends [[sv_prefix_proposal]] to cover multiple
 registers.  The basic principle: the "prefix" specifies which of source and
 destination registers are to be considered "vectors" (or scalars), however
 where in SVPrefix that applies to only one instruction, the "vector" tag
-designations *continue to cascade* into subsequent instructions within the
+designations *continue a limited cascade* into subsequent instructions within the
 VBLOCK.
 
 Its advantage over the main format is that the main format requires