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[libreriscv.git] / simple_v_extension / vblock_format.mdwn

diff --git a/simple_v_extension/vblock_format.mdwn b/simple_v_extension/vblock_format.mdwn
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--- a/simple_v_extension/vblock_format.mdwn
+++ b/simple_v_extension/vblock_format.mdwn
@@ -1,15 +1,17 @@
+[[!tag standards]]
+
 # Simple-V (Parallelism Extension Proposal) Vector Block Format
 
 * Copyright (C) 2017, 2018, 2019 Luke Kenneth Casson Leighton
-* Status: DRAFTv0.7
-* Last edited: 30 aug 2019
+* Status: DRAFTv0.7.1
+* Last edited: 2 sep 2019
 
 [[!toc ]]
 
 # Vector Block Format <a name="vliw-format"></a>
 
 This is a way to give Vector and Predication Context to a group of
-standard scalar RISC-V instructions, in a highly compact form.
+standard scalar RISC-V instructions, in a highly compact form. Program Execution Order is still preserved (unlike VLIW), just with "context" that would otherwise require much longer instructions.
 
 The format is:
 
@@ -151,6 +153,46 @@ The swizzle table format is included here for convenience:
 
 Swizzle blocks are only accessible using the "VBLOCK2" format.
 
+The swizzles activate on SUBVL and only when used in an operation where a register matches with a SwizzleCAM register entry.
+
+On a match the register element index will be redirected through the swizzle format. If however the type is set to "constants" then instead of reading the register file the relevant constant is substituted instead.
+
+Setting const type on a destination element will cause an illegal instruction.
+
+
+# REMAP Area Format<a name="remap_format"></a>
+
+REMAP is an algorithmic version of in-place vector "vgather" or "swizzle".
+
+The REMAP area is divided into two areas:
+
+* Register-to-SHAPE.  This defines which registers have which shapes.
+  Each entry is 8-bits in length.
+* SHAPE Table entries.  These are 32-bits in length and are aligned
+  to (start on) a 16 bit boundary.
+
+REMAP Table Entries:
+
+| 7:5      | 4:0    |
+| -------- | ------ |
+| shapeidx | regnum |
+
+When both shapeidx and regnum are zero, this indicates the end of the
+REMAP Register-to-SHAPE section.  The REMAP Table section size is then
+aligned to a 16-bit boundary.  32-bit SHAPE Table Entries then fill the
+remainder of the REMAP area, and are indexed in order by shapeidx.
+
+In this way, multiple registers may share the same "shape" characteristics.
+
+# SHAPE Table Format<a name="shape_format"></a>
+
+The shape table format is included here for convenience. See [[simple_v_extension/remap]] for full details on how SHAPE applies,
+including pseudo-code.
+
+[[!inline raw="yes" pages="simple_v_extension/shape_table_format" ]]
+
+REMAP Shape blocks are only accessible using the "VBLOCK2" format.
+
 # CSRs:
 
 The CSRs needed, in addition to those from the main [[specification]] are: