immed in same 6 bits

[libreriscv.git] / simple_v_extension / vblock_format_table.mdwn

diff --git a/simple_v_extension/vblock_format_table.mdwn b/simple_v_extension/vblock_format_table.mdwn
index 04eb54e775e7a4f792203aed6c51ca2c77afaa1a..97b81209297a68e98b15763311367fb9830df8bc 100644 (file)
--- a/simple_v_extension/vblock_format_table.mdwn
+++ b/simple_v_extension/vblock_format_table.mdwn
@@ -13,8 +13,11 @@ of the RISC-V ISA, is as follows:
 
 The VL/MAXVL/SubVL Block format:
 
-| 31-30 | 29:28 | 27:22  | 21:17  - 16  |
-| -     | ----- | ------ | ------ - -   |
-| 0     | SubVL | VLdest | VLEN     vlt |
-| 1     | SubVL | VLdest | VLEN         |
+[[!table  data="""
+31:30 | 29:28 | 27:22  | 21 | 20:19   | 18:16    | comment              |
+0b00  | SubVL |imm[5:0]|rsvd| rd[4:0]           || VL set from imm      |
+0b01  | SubVL |imm[5:0]| rs1[2:0]    || rd[2:0]  | RVC reg format       |
+0b10  | SubVL |imm[5:0]|rsvd|   rd[4:0]     || VL & MVL set from imm|
+0b11  | rsvd  | rsvd   |rsvd|      rsvd     || reserved, all 0s     |
+"""]]