Merge pull request #113 from mikey/exec-sim-remove

[microwatt.git] / soc.vhdl

diff --git a/soc.vhdl b/soc.vhdl
index 735d86ccc584fcb79eaa641b8685df9b66bf002a..94ab39366c5e68942f22a12a6b76f8a6c2c760c1 100644 (file)
--- a/soc.vhdl
+++ b/soc.vhdl
@@ -1,8 +1,9 @@
 library ieee;
 use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
 use ieee.math_real.all;
-
 use std.textio.all;
+use std.env.stop;
 
 library work;
 use work.common.all;
@@ -24,7 +25,10 @@ entity soc is
 
        -- UART0 signals:
        uart0_txd    : out std_ulogic;
-       uart0_rxd    : in  std_ulogic
+       uart0_rxd    : in  std_ulogic;
+
+       -- Misc (to use for things like LEDs)
+       core_terminated : out std_ulogic
        );
 end entity soc;
 
@@ -52,10 +56,6 @@ architecture behaviour of soc is
     signal wb_bram_out    : wishbone_slave_out;
     constant mem_adr_bits : positive := positive(ceil(log2(real(MEMORY_SIZE))));
 
-    -- Core debug signals (used in SIM only)
-    signal registers     : regfile;
-    signal terminate     : std_ulogic;
-
     -- DMI debug bus signals
     signal dmi_addr    : std_ulogic_vector(7 downto 0);
     signal dmi_din     : std_ulogic_vector(63 downto 0);
@@ -64,6 +64,13 @@ architecture behaviour of soc is
     signal dmi_wr      : std_ulogic;
     signal dmi_ack     : std_ulogic;
 
+    -- Per slave DMI signals
+    signal dmi_wb_dout  : std_ulogic_vector(63 downto 0);
+    signal dmi_wb_req   : std_ulogic;
+    signal dmi_wb_ack   : std_ulogic;
+    signal dmi_core_dout  : std_ulogic_vector(63 downto 0);
+    signal dmi_core_req   : std_ulogic;
+    signal dmi_core_ack   : std_ulogic;
 begin
 
     -- Processor core
@@ -78,8 +85,12 @@ begin
            wishbone_insn_out => wishbone_icore_out,
            wishbone_data_in => wishbone_dcore_in,
            wishbone_data_out => wishbone_dcore_out,
-           registers => registers,
-           terminate_out => terminate
+           dmi_addr => dmi_addr(3 downto 0),
+           dmi_dout => dmi_core_dout,
+           dmi_din => dmi_dout,
+           dmi_wr => dmi_wr,
+           dmi_ack => dmi_core_ack,
+           dmi_req => dmi_core_req
            );
 
     -- Wishbone bus master arbiter & mux
@@ -92,14 +103,10 @@ begin
            wb_out => wb_master_out, wb_in => wb_master_in
            );
 
-    -- Dummy wishbone debug module
-    wishbone_debug_out.cyc <= '0';
-    wishbone_debug_out.stb <= '0';
-
     -- Wishbone slaves address decoder & mux
     slave_intercon: process(wb_master_out, wb_bram_out, wb_uart0_out)
        -- Selected slave
-       type slave_type is (SLAVE_UART,
+       type slave_type is (SLAVE_UART_0,
                            SLAVE_MEMORY,
                            SLAVE_NONE);
        variable slave : slave_type;
@@ -109,8 +116,8 @@ begin
        if wb_master_out.adr(63 downto 24) = x"0000000000" then
            slave := SLAVE_MEMORY;
        elsif wb_master_out.adr(63 downto 24) = x"00000000c0" then
-           if wb_master_out.adr(15 downto 12) = x"2" then
-               slave := SLAVE_UART;
+           if wb_master_out.adr(23 downto 12) = x"002" then
+               slave := SLAVE_UART_0;
            end if;
        end if;
 
@@ -123,7 +130,7 @@ begin
        when SLAVE_MEMORY =>
            wb_bram_in.cyc <= wb_master_out.cyc;
            wb_master_in <= wb_bram_out;
-       when SLAVE_UART =>
+       when SLAVE_UART_0 =>
            wb_uart0_in.cyc <= wb_master_out.cyc;
            wb_master_in <= wb_uart0_out;
        when others =>
@@ -133,20 +140,6 @@ begin
     end process slave_intercon;
 
     -- Simulated memory and UART
-    sim_terminate_test: if SIM generate
-
-       -- Dump registers if core terminates
-       dump_registers: process(all)
-       begin
-           if terminate = '1' then
-               loop_0: for i in 0 to 31 loop
-                   report "REG " & to_hstring(registers(i));
-               end loop loop_0;
-               assert false report "end of test" severity failure;
-           end if;
-       end process;
-
-    end generate;
 
     -- UART0 wishbone slave
     -- XXX FIXME: Need a proper wb64->wb8 adapter that
@@ -202,8 +195,64 @@ begin
            dmi_ack     => dmi_ack
            );
 
-    -- Dummy loopback until a debug module is present
-    dmi_din <= dmi_dout;
-    dmi_ack <= dmi_ack;
+    -- DMI interconnect
+    dmi_intercon: process(dmi_addr, dmi_req,
+                         dmi_wb_ack, dmi_wb_dout,
+                         dmi_core_ack, dmi_core_dout)
+
+       -- DMI address map (each address is a full 64-bit register)
+       --
+       -- Offset:   Size:    Slave:
+       --  0         4       Wishbone
+       -- 10        16       Core
+
+       type slave_type is (SLAVE_WB,
+                           SLAVE_CORE,
+                           SLAVE_NONE);
+       variable slave : slave_type;
+    begin
+       -- Simple address decoder
+       slave := SLAVE_NONE;
+       if std_match(dmi_addr, "000000--") then
+           slave := SLAVE_WB;
+       elsif std_match(dmi_addr, "0001----") then
+           slave := SLAVE_CORE;
+       end if;
+
+       -- DMI muxing
+       dmi_wb_req <= '0';
+       dmi_core_req <= '0';
+       case slave is
+       when SLAVE_WB =>
+           dmi_wb_req <= dmi_req;
+           dmi_ack <= dmi_wb_ack;
+           dmi_din <= dmi_wb_dout;
+       when SLAVE_CORE =>
+           dmi_core_req <= dmi_req;
+           dmi_ack <= dmi_core_ack;
+           dmi_din <= dmi_core_dout;
+       when others =>
+           dmi_ack <= dmi_req;
+           dmi_din <= (others => '1');
+       end case;
+
+       -- SIM magic exit
+       if SIM and dmi_req = '1' and dmi_addr = "11111111" and dmi_wr = '1' then
+           stop;
+       end if;
+    end process;
+
+    -- Wishbone debug master (TODO: Add a DMI address decoder)
+    wishbone_debug: entity work.wishbone_debug_master
+       port map(clk => system_clk, rst => rst,
+                dmi_addr => dmi_addr(1 downto 0),
+                dmi_dout => dmi_wb_dout,
+                dmi_din => dmi_dout,
+                dmi_wr => dmi_wr,
+                dmi_ack => dmi_wb_ack,
+                dmi_req => dmi_wb_req,
+                wb_in => wishbone_debug_in,
+                wb_out => wishbone_debug_out);
+
 
 end architecture behaviour;