# Copyright (C) Jonathan P Dawson 2013
# 2013-12-12
-from nmigen import Signal, Cat, Const, Mux, Module
+from nmigen import Signal, Cat, Const, Mux, Module, Elaboratable
from math import log
from operator import or_
from functools import reduce
return res
-class FPNumBase:
+class FPNumBase: #(Elaboratable):
""" Floating-point Base Number Class
"""
def __init__(self, width, m_extra=True):
return self.create2(s, self.N127, self.mzero)
-class MultiShiftRMerge:
+class MultiShiftRMerge(Elaboratable):
""" shifts down (right) and merges lower bits into m[0].
m[0] is the "sticky" bit, basically
"""
return m
-class FPNumShift(FPNumBase):
+class FPNumShift(FPNumBase, Elaboratable):
""" Floating-point Number Class for shifting
"""
def __init__(self, mainm, op, inv, width, m_extra=True):
self.m.eq(sm.lshift(self.m, maxslen))
]
-class Trigger:
+class Trigger(Elaboratable):
def __init__(self):
self.stb = Signal(reset=0)
PrevControl.__init__(self)
self.width = width
self.v = Signal(width)
- self.i_data = self.v
+ self.data_i = self.v
def chain_inv(self, in_op, extra=None):
stb = in_op.stb
NextControl.__init__(self)
self.width = width
self.v = Signal(width)
- self.o_data = self.v
+ self.data_o = self.v
def chain_inv(self, in_op, extra=None):
stb = in_op.stb
]
-class Overflow:
+class Overflow: #(Elaboratable):
def __init__(self):
self.guard = Signal(reset_less=True) # tot[2]
self.round_bit = Signal(reset_less=True) # tot[1]
"""
res = v.decode2(m)
ack = Signal()
- with m.If((op.o_ready) & (op.i_valid_test)):
+ with m.If((op.ready_o) & (op.valid_i_test)):
m.next = next_state
# op is latched in from FPNumIn class on same ack/stb
m.d.comb += ack.eq(0)
m.d.sync += [
out_z.v.eq(z.v)
]
- with m.If(out_z.o_valid & out_z.i_ready_test):
- m.d.sync += out_z.o_valid.eq(0)
+ with m.If(out_z.valid_o & out_z.ready_i_test):
+ m.d.sync += out_z.valid_o.eq(0)
m.next = next_state
with m.Else():
- m.d.sync += out_z.o_valid.eq(1)
+ m.d.sync += out_z.valid_o.eq(1)
class FPState(FPBase):