UINT_32 preferEquation : 1; ///< Return equation index without adjusting tile mode
UINT_32 matchStencilTileCfg : 1; ///< Select tile index of stencil as well as depth surface
/// to make sure they share same tile config parameters
- UINT_32 reserved : 3; ///< Reserved bits
+ UINT_32 disallowLargeThickDegrade : 1; ///< Disallow large thick tile degrade
+ UINT_32 reserved : 1; ///< Reserved bits
};
UINT_32 value;
};
UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE
};
-
-#if ADDR_AM_BUILD // These two fields are not valid in SW blt since no HTILE access
- UINT_32 addr5Swizzle; ///< ADDR5_SWIZZLE_MASK of DB_DEPTH_INFO
- BOOL_32 is32ByteTile; ///< Caller must have access to HTILE buffer and know if
- /// this tile is compressed to 32B
-#endif
} ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT;
/**
{
struct
{
- UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable
- UINT_32 reserved :31; ///< Reserved bits
+ UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable
+ UINT_32 skipTcCompatSizeAlign : 1; ///< Flag indicates that addrLib will not align htile
+ /// size to 256xBankxPipe when computing tc-compatible
+ /// htile info.
+ UINT_32 reserved : 30; ///< Reserved bits
};
UINT_32 value;
UINT_64 sliceSize; ///< Slice size, in bytes.
BOOL_32 sliceInterleaved; ///< Flag to indicate if different slice's htile is interleaved
/// Compute engine clear can't be used if htile is interleaved
+ BOOL_32 nextMipLevelCompressible; ///< Flag to indicate whether HTILE can be enabled in
+ /// next mip level, it also indicates if memory set based
+ /// fast clear can be used for current mip level.
} ADDR_COMPUTE_HTILE_INFO_OUTPUT;
/**
-
/**
****************************************************************************************************
* ADDR_PRT_INFO_INPUT
const ADDR_PRT_INFO_INPUT* pIn,
ADDR_PRT_INFO_OUTPUT* pOut);
+
+
////////////////////////////////////////////////////////////////////////////////////////////////////
// DCC key functions
////////////////////////////////////////////////////////////////////////////////////////////////////
typedef struct _ADDR_COMPUTE_DCCINFO_OUTPUT
{
UINT_32 size; ///< Size of this structure in bytes
- UINT_64 dccRamBaseAlign; ///< Base alignment of dcc key
+ UINT_32 dccRamBaseAlign; ///< Base alignment of dcc key
UINT_64 dccRamSize; ///< Size of dcc key
UINT_64 dccFastClearSize; ///< Size of dcc key portion that can be fast cleared
BOOL_32 subLvlCompressible; ///< Whether sub resource is compressiable
const ADDR_COMPUTE_DCCINFO_INPUT* pIn,
ADDR_COMPUTE_DCCINFO_OUTPUT* pOut);
+
+
/**
****************************************************************************************************
* ADDR_GET_MAX_ALINGMENTS_OUTPUT
typedef struct _ADDR_GET_MAX_ALINGMENTS_OUTPUT
{
UINT_32 size; ///< Size of this structure in bytes
- UINT_64 baseAlign; ///< Maximum base alignment in bytes
+ UINT_32 baseAlign; ///< Maximum base alignment in bytes
} ADDR_GET_MAX_ALINGMENTS_OUTPUT;
/**
ADDR_HANDLE hLib,
ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut);
-
+/**
+****************************************************************************************************
+* AddrGetMaxMetaAlignments
+*
+* @brief
+* Gets maximnum alignments for metadata
+****************************************************************************************************
+*/
+ADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments(
+ ADDR_HANDLE hLib,
+ ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut);
/**
****************************************************************************************************
{
struct
{
- UINT_32 color : 1; ///< This resource is a color buffer, can be used with RTV
- UINT_32 depth : 1; ///< Thie resource is a depth buffer, can be used with DSV
- UINT_32 stencil : 1; ///< Thie resource is a stencil buffer, can be used with DSV
- UINT_32 fmask : 1; ///< This is an fmask surface
- UINT_32 overlay : 1; ///< This is an overlay surface
- UINT_32 display : 1; ///< This resource is displable, can be used with DRV
- UINT_32 prt : 1; ///< This is a partially resident texture
- UINT_32 qbStereo : 1; ///< This is a quad buffer stereo surface
- UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding
- UINT_32 texture : 1; ///< This resource can be used with SRV
- UINT_32 unordered : 1; ///< This resource can be used with UAV
- UINT_32 rotated : 1; ///< This resource is rotated and displable
- UINT_32 needEquation : 1; ///< This resource needs equation to be generated if possible
- UINT_32 opt4space : 1; ///< This resource should be optimized for space
- UINT_32 minimizeAlign : 1; ///< This resource should use minimum alignment
- UINT_32 reserved : 17; ///< Reserved bits
+ UINT_32 color : 1; ///< This resource is a color buffer, can be used with RTV
+ UINT_32 depth : 1; ///< Thie resource is a depth buffer, can be used with DSV
+ UINT_32 stencil : 1; ///< Thie resource is a stencil buffer, can be used with DSV
+ UINT_32 fmask : 1; ///< This is an fmask surface
+ UINT_32 overlay : 1; ///< This is an overlay surface
+ UINT_32 display : 1; ///< This resource is displable, can be used with DRV
+ UINT_32 prt : 1; ///< This is a partially resident texture
+ UINT_32 qbStereo : 1; ///< This is a quad buffer stereo surface
+ UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding
+ UINT_32 texture : 1; ///< This resource can be used with SRV
+ UINT_32 unordered : 1; ///< This resource can be used with UAV
+ UINT_32 rotated : 1; ///< This resource is rotated and displable
+ UINT_32 needEquation : 1; ///< This resource needs equation to be generated if possible
+ UINT_32 opt4space : 1; ///< This resource should be optimized for space
+ UINT_32 minimizeAlign : 1; ///< This resource should use minimum alignment
+ UINT_32 noMetadata : 1; ///< This resource has no metadata
+ UINT_32 metaRbUnaligned : 1; ///< This resource has rb unaligned metadata
+ UINT_32 metaPipeUnaligned : 1; ///< This resource has pipe unaligned metadata
+ UINT_32 reserved : 14; ///< Reserved bits
};
UINT_32 value;
UINT_32 pitch; ///< Pitch in elements
UINT_32 height; ///< Padded height in elements
UINT_32 depth; ///< Padded depth
- UINT_32 offset; ///< Offset in bytes from mip base
-
+ UINT_32 pixelPitch; ///< Pitch in pixels
+ UINT_32 pixelHeight; ///< Padded height in pixels
UINT_32 equationIndex; ///< Equation index in the equation table
- UINT_32 mipOffsetXBytes; ///< Mip start position offset in byte in X direction
- UINT_32 mipOffsetYPixel; ///< Mip start position offset in pixel in Y direction
- UINT_32 mipOffsetZPixel; ///< Mip start position offset in pixel in Z direction
- UINT_32 postSwizzleOffset; ///< Offset which is used to be added directly onto
- /// the address calculated by equation
+ UINT_64 offset; ///< Offset in bytes from mip base, should only be used
+ ///< to setup vam surface descriptor, can't be used
+ ///< to setup swizzle pattern
+ UINT_64 macroBlockOffset; ///< macro block offset in bytes from mip base
+ UINT_32 mipTailOffset; ///< mip tail offset in bytes
+ UINT_32 mipTailCoordX; ///< mip tail coord x
+ UINT_32 mipTailCoordY; ///< mip tail coord y
+ UINT_32 mipTailCoordZ; ///< mip tail coord z
} ADDR2_MIP_INFO;
/**
UINT_32 mipChainPitch; ///< Pitch (of total mip chain) in elements
UINT_32 mipChainHeight; ///< Padded height (of total mip chain) in elements
UINT_32 mipChainSlice; ///< Padded depth (of total mip chain)
- UINT_32 sliceSize; ///< Slice (total mip chain) size in bytes
+ UINT_64 sliceSize; ///< Slice (total mip chain) size in bytes
UINT_64 surfSize; ///< Surface (total mip chain) size in bytes
UINT_32 baseAlign; ///< Base address alignment
UINT_32 bpp; ///< Bits per elements
/// contain numMipLevels entries
UINT_32 equationIndex; ///< Equation index in the equation table of mip0
- BOOL_32 firstMipInTail; ///< If whole mipchain falls into mip tail block
+ BOOL_32 mipChainInTail; ///< If whole mipchain falls into mip tail block
+ UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if there is no mip
+ /// in tail, it will be set to number of mip levels
} ADDR2_COMPUTE_SURFACE_INFO_OUTPUT;
/**
typedef struct _ADDR2_META_MIP_INFO
{
BOOL_32 inMiptail;
- UINT_32 startX;
- UINT_32 startY;
- UINT_32 startZ;
- UINT_32 width;
- UINT_32 height;
- UINT_32 depth;
+ union
+ {
+ struct
+ {
+ UINT_32 startX;
+ UINT_32 startY;
+ UINT_32 startZ;
+ UINT_32 width;
+ UINT_32 height;
+ UINT_32 depth;
+ };
+
+ struct
+ {
+ UINT_32 offset;
+ UINT_32 sliceSize;
+ };
+ };
} ADDR2_META_MIP_INFO;
/**
UINT_32 unalignedHeight; ///< Depth surface original height (of mip0)
UINT_32 numSlices; ///< Number of slices of depth surface (of mip0)
UINT_32 numMipLevels; ///< Total mipmap levels of color surface
+ UINT_32 firstMipIdInTail;
} ADDR2_COMPUTE_HTILE_INFO_INPUT;
/**
UINT_32 unalignedHeight; ///< Color surface original height
UINT_32 numSamples; ///< Number of samples
UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
- /// number of samples for normal AA; Set it to the
- /// number of fragments for EQAA
+ /// number of samples for normal AA; Set it to the
+ /// number of fragments for EQAA
UINT_32 tileSwizzle; ///< Combined swizzle used to do bank/pipe rotation
ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags
UINT_32 numMipLevels; ///< Total mipmap levels of color surface
UINT_32 dataSurfaceSize; ///< The padded size of all slices and mip levels
///< useful in meta linear case
+ UINT_32 firstMipIdInTail;
} ADDR2_COMPUTE_DCCINFO_INPUT;
/**
UINT_32 metaBlkHeight; ///< DCC meta block height
UINT_32 metaBlkDepth; ///< DCC meta block depth
- UINT_32 fastClearSizePerSlice; ///< Size of DCC within a slice should be fast cleared
- UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice
+ UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice
+
+ union
+ {
+ UINT_32 fastClearSizePerSlice; ///< Size of DCC within a slice should be fast cleared
+ UINT_32 dccRamSliceSize;
+ };
ADDR2_META_MIP_INFO* pMipInfo; ///< DCC mip information
} ADDR2_COMPUTE_DCCINFO_OUTPUT;
ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut);
+/**
+****************************************************************************************************
+* ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT
+*
+* @brief
+* Input structure for Addr2ComputeDccAddrFromCoord
+*
+****************************************************************************************************
+*/
+typedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT
+{
+ UINT_32 size; ///< Size of this structure in bytes
+
+ UINT_32 x; ///< X coordinate
+ UINT_32 y; ///< Y coordinate
+ UINT_32 slice; ///< Index of slices
+ UINT_32 sample; ///< Index of samples, means fragment index for EQAA
+ UINT_32 mipId; ///< mipmap level id
+
+ ADDR2_META_FLAGS dccKeyFlags; ///< DCC flags
+ ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
+ AddrResourceType resourceType; ///< Color surface type
+ AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode
+ UINT_32 bpp; ///< Color surface bits per pixel
+ UINT_32 unalignedWidth; ///< Color surface original width (of mip0)
+ UINT_32 unalignedHeight; ///< Color surface original height (of mip0)
+ UINT_32 numSlices; ///< Color surface original slices (of mip0)
+ UINT_32 numMipLevels; ///< Color surface mipmap levels
+ UINT_32 numFrags; ///< Color surface fragment number
+
+ UINT_32 pipeXor; ///< pipe Xor setting
+} ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT;
+
+/**
+****************************************************************************************************
+* ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT
+*
+* @brief
+* Output structure for Addr2ComputeDccAddrFromCoord
+****************************************************************************************************
+*/
+typedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT
+{
+ UINT_32 size; ///< Size of this structure in bytes
+
+ UINT_64 addr; ///< DCC address in bytes
+} ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT;
+
+/**
+****************************************************************************************************
+* Addr2ComputeDccAddrFromCoord
+*
+* @brief
+* Compute DCC address according to coordinates (of MSAA color buffer)
+****************************************************************************************************
+*/
+ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccAddrFromCoord(
+ ADDR_HANDLE hLib,
+ const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
+ ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut);
////////////////////////////////////////////////////////////////////////////////////////////////////
// Misc functions for Gfx9
ADDR2_SURFACE_FLAGS flags; ///< Surface flag
AddrSwizzleMode swizzleMode; ///< Surface swizzle mode
AddrResourceType resourceType; ///< Surface resource type
+ AddrFormat format; ///< Surface format
+ UINT_32 numSamples; ///< Number of samples
+ UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
+ /// number of samples for normal AA; Set it to the
+ /// number of fragments for EQAA
} ADDR2_COMPUTE_PIPEBANKXOR_INPUT;
/**
const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn,
ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut);
+/**
+****************************************************************************************************
+* ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT
+*
+* @brief
+* Input structure of Addr2ComputeSlicePipeBankXor
+****************************************************************************************************
+*/
+typedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT
+{
+ UINT_32 size; ///< Size of this structure in bytes
+ AddrSwizzleMode swizzleMode; ///< Surface swizzle mode
+ AddrResourceType resourceType; ///< Surface resource type
+ UINT_32 basePipeBankXor; ///< Base pipe bank xor
+ UINT_32 slice; ///< Slice id
+ UINT_32 numSamples; ///< Number of samples
+} ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT;
+
+/**
+****************************************************************************************************
+* ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT
+*
+* @brief
+* Output structure of Addr2ComputeSlicePipeBankXor
+****************************************************************************************************
+*/
+typedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT
+{
+ UINT_32 size; ///< Size of this structure in bytes
+ UINT_32 pipeBankXor; ///< Pipe bank xor
+} ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT;
+
+/**
+****************************************************************************************************
+* Addr2ComputeSlicePipeBankXor
+*
+* @brief
+* Calculate slice pipe bank xor value based on base pipe bank xor and slice id.
+****************************************************************************************************
+*/
+ADDR_E_RETURNCODE ADDR_API Addr2ComputeSlicePipeBankXor(
+ ADDR_HANDLE hLib,
+ const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
+ ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut);
+
+/**
+****************************************************************************************************
+* ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT
+*
+* @brief
+* Input structure of Addr2ComputeSubResourceOffsetForSwizzlePattern
+****************************************************************************************************
+*/
+typedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT
+{
+ UINT_32 size; ///< Size of this structure in bytes
+ AddrSwizzleMode swizzleMode; ///< Surface swizzle mode
+ AddrResourceType resourceType; ///< Surface resource type
+ UINT_32 pipeBankXor; ///< Per resource xor
+ UINT_32 slice; ///< Slice id
+ UINT_64 sliceSize; ///< Slice size of a mip chain
+ UINT_64 macroBlockOffset; ///< Macro block offset, returned in ADDR2_MIP_INFO
+ UINT_32 mipTailOffset; ///< Mip tail offset, returned in ADDR2_MIP_INFO
+} ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT;
+
+/**
+****************************************************************************************************
+* ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT
+*
+* @brief
+* Output structure of Addr2ComputeSubResourceOffsetForSwizzlePattern
+****************************************************************************************************
+*/
+typedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT
+{
+ UINT_32 size; ///< Size of this structure in bytes
+ UINT_64 offset; ///< offset
+} ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT;
+/**
+****************************************************************************************************
+* Addr2ComputeSubResourceOffsetForSwizzlePattern
+*
+* @brief
+* Calculate sub resource offset to support swizzle pattern.
+****************************************************************************************************
+*/
+ADDR_E_RETURNCODE ADDR_API Addr2ComputeSubResourceOffsetForSwizzlePattern(
+ ADDR_HANDLE hLib,
+ const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
+ ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut);
/**
****************************************************************************************************
* ADDR2_BLOCK_SET
*
* @brief
-* Bit field that define block type
+* Bit field that defines block type
****************************************************************************************************
*/
typedef union _ADDR2_BLOCK_SET
UINT_32 value;
} ADDR2_BLOCK_SET;
+/**
+****************************************************************************************************
+* ADDR2_SWTYPE_SET
+*
+* @brief
+* Bit field that defines swizzle type
+****************************************************************************************************
+*/
+typedef union _ADDR2_SWTYPE_SET
+{
+ struct
+ {
+ UINT_32 sw_Z : 1; // SW_*_Z_*
+ UINT_32 sw_S : 1; // SW_*_S_*
+ UINT_32 sw_D : 1; // SW_*_D_*
+ UINT_32 sw_R : 1; // SW_*_R_*
+ UINT_32 reserved : 28;
+ };
+
+ UINT_32 value;
+} ADDR2_SWTYPE_SET;
+
/**
****************************************************************************************************
* ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
AddrResrouceLocation resourceLoction; ///< Surface heap choice
ADDR2_BLOCK_SET forbiddenBlock; ///< Client can use it to disable some block setting
///< such as linear for DXTn, tiled for YUV
+ ADDR2_SWTYPE_SET preferredSwSet; ///< Client can use it to specify sw type(s) wanted
BOOL_32 noXor; ///< Do not use xor mode for this resource
UINT_32 bpp; ///< bits per pixel
UINT_32 width; ///< Width (of mip0), in pixels
/// number of samples for normal AA; Set it to the
/// number of fragments for EQAA
UINT_32 maxAlign; ///< maximum base/size alignment requested by client
+ UINT_32 minSizeAlign; ///< memory allocated for surface in client driver will
+ /// be padded to multiple of this value (in bytes)
} ADDR2_GET_PREFERRED_SURF_SETTING_INPUT;
/**
*/
typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT
{
- UINT_32 size; ///< Size of this structure in bytes
+ UINT_32 size; ///< Size of this structure in bytes
- AddrSwizzleMode swizzleMode; ///< Suggested swizzle mode to be used
- AddrResourceType resourceType; ///< Suggested resource type to program HW
- ADDR2_BLOCK_SET validBlockSet; ///< Valid block type bit conbination
- BOOL_32 canXor; ///< If client can use xor on a valid macro block type
+ AddrSwizzleMode swizzleMode; ///< Suggested swizzle mode to be used
+ AddrResourceType resourceType; ///< Suggested resource type to program HW
+ ADDR2_BLOCK_SET validBlockSet; ///< Valid block type bit conbination
+ BOOL_32 canXor; ///< If client can use xor on a valid macro block
+ /// type
+ ADDR2_SWTYPE_SET validSwTypeSet; ///< Valid swizzle type bit combination
+ ADDR2_SWTYPE_SET clientPreferredSwSet; ///< Client-preferred swizzle type bit combination
} ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT;
/**
const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut);
+/**
+****************************************************************************************************
+* Addr2IsValidDisplaySwizzleMode
+*
+* @brief
+* Return whether the swizzle mode is supported by DCE / DCN.
+****************************************************************************************************
+*/
+ADDR_E_RETURNCODE ADDR_API Addr2IsValidDisplaySwizzleMode(
+ ADDR_HANDLE hLib,
+ AddrSwizzleMode swizzleMode,
+ UINT_32 bpp,
+ bool *result);
+
#if defined(__cplusplus)
}
#endif
projects / mesa.git / blobdiff