*/
/**
-***************************************************************************************************
+****************************************************************************************************
* @file addrlib.h
-* @brief Contains the AddrLib base class definition.
-***************************************************************************************************
+* @brief Contains the Addr::Lib base class definition.
+****************************************************************************************************
*/
#ifndef __ADDR_LIB_H__
#define __ADDR_LIB_H__
-
#include "addrinterface.h"
#include "addrobject.h"
#include "addrelemlib.h"
-#if BRAHMA_BUILD
-#include "amdgpu_id.h"
-#else
-#include "atiid.h"
-#endif
+#include "amdgpu_asic_addr.h"
#ifndef CIASICIDGFXENGINE_R600
#define CIASICIDGFXENGINE_R600 0x00000006
#define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
#endif
-#ifndef CIASICIDGFXENGINE_SEAISLAND
-#define CIASICIDGFXENGINE_SEAISLAND 0x0000000B
+#ifndef CIASICIDGFXENGINE_ARCTICISLAND
+#define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
#endif
+
+namespace Addr
+{
+
/**
-***************************************************************************************************
+****************************************************************************************************
* @brief Neutral enums that define pipeinterleave
-***************************************************************************************************
+****************************************************************************************************
*/
-enum AddrPipeInterleave
+enum PipeInterleave
{
ADDR_PIPEINTERLEAVE_256B = 256,
ADDR_PIPEINTERLEAVE_512B = 512,
+ ADDR_PIPEINTERLEAVE_1KB = 1024,
+ ADDR_PIPEINTERLEAVE_2KB = 2048,
};
/**
-***************************************************************************************************
+****************************************************************************************************
* @brief Neutral enums that define DRAM row size
-***************************************************************************************************
+****************************************************************************************************
*/
-enum AddrRowSize
+enum RowSize
{
ADDR_ROWSIZE_1KB = 1024,
ADDR_ROWSIZE_2KB = 2048,
};
/**
-***************************************************************************************************
+****************************************************************************************************
* @brief Neutral enums that define bank interleave
-***************************************************************************************************
+****************************************************************************************************
*/
-enum AddrBankInterleave
+enum BankInterleave
{
ADDR_BANKINTERLEAVE_1 = 1,
ADDR_BANKINTERLEAVE_2 = 2,
};
/**
-***************************************************************************************************
-* @brief Neutral enums that define MGPU chip tile size
-***************************************************************************************************
-*/
-enum AddrChipTileSize
-{
- ADDR_CHIPTILESIZE_16 = 16,
- ADDR_CHIPTILESIZE_32 = 32,
- ADDR_CHIPTILESIZE_64 = 64,
- ADDR_CHIPTILESIZE_128 = 128,
-};
-
-/**
-***************************************************************************************************
+****************************************************************************************************
* @brief Neutral enums that define shader engine tile size
-***************************************************************************************************
+****************************************************************************************************
*/
-enum AddrEngTileSize
+enum ShaderEngineTileSize
{
ADDR_SE_TILESIZE_16 = 16,
ADDR_SE_TILESIZE_32 = 32,
};
/**
-***************************************************************************************************
+****************************************************************************************************
* @brief Neutral enums that define bank swap size
-***************************************************************************************************
+****************************************************************************************************
*/
-enum AddrBankSwapSize
+enum BankSwapSize
{
ADDR_BANKSWAP_128B = 128,
ADDR_BANKSWAP_256B = 256,
ADDR_BANKSWAP_1KB = 1024,
};
+/**
+****************************************************************************************************
+* @brief Enums that define max compressed fragments config
+****************************************************************************************************
+*/
+enum NumMaxCompressedFragmentsConfig
+{
+ ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0x00000000,
+ ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 0x00000001,
+ ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 0x00000002,
+ ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 0x00000003,
+};
+
+/**
+****************************************************************************************************
+* @brief Enums that define num pipes config
+****************************************************************************************************
+*/
+enum NumPipesConfig
+{
+ ADDR_CONFIG_1_PIPE = 0x00000000,
+ ADDR_CONFIG_2_PIPE = 0x00000001,
+ ADDR_CONFIG_4_PIPE = 0x00000002,
+ ADDR_CONFIG_8_PIPE = 0x00000003,
+ ADDR_CONFIG_16_PIPE = 0x00000004,
+ ADDR_CONFIG_32_PIPE = 0x00000005,
+ ADDR_CONFIG_64_PIPE = 0x00000006,
+};
+
+/**
+****************************************************************************************************
+* @brief Enums that define num banks config
+****************************************************************************************************
+*/
+enum NumBanksConfig
+{
+ ADDR_CONFIG_1_BANK = 0x00000000,
+ ADDR_CONFIG_2_BANK = 0x00000001,
+ ADDR_CONFIG_4_BANK = 0x00000002,
+ ADDR_CONFIG_8_BANK = 0x00000003,
+ ADDR_CONFIG_16_BANK = 0x00000004,
+};
+
+/**
+****************************************************************************************************
+* @brief Enums that define num rb per shader engine config
+****************************************************************************************************
+*/
+enum NumRbPerShaderEngineConfig
+{
+ ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0x00000000,
+ ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 0x00000001,
+ ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 0x00000002,
+};
+
+/**
+****************************************************************************************************
+* @brief Enums that define num shader engines config
+****************************************************************************************************
+*/
+enum NumShaderEnginesConfig
+{
+ ADDR_CONFIG_1_SHADER_ENGINE = 0x00000000,
+ ADDR_CONFIG_2_SHADER_ENGINE = 0x00000001,
+ ADDR_CONFIG_4_SHADER_ENGINE = 0x00000002,
+ ADDR_CONFIG_8_SHADER_ENGINE = 0x00000003,
+};
+
+/**
+****************************************************************************************************
+* @brief Enums that define pipe interleave size config
+****************************************************************************************************
+*/
+enum PipeInterleaveSizeConfig
+{
+ ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x00000000,
+ ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x00000001,
+ ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 0x00000002,
+ ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 0x00000003,
+};
+
+/**
+****************************************************************************************************
+* @brief Enums that define row size config
+****************************************************************************************************
+*/
+enum RowSizeConfig
+{
+ ADDR_CONFIG_1KB_ROW = 0x00000000,
+ ADDR_CONFIG_2KB_ROW = 0x00000001,
+ ADDR_CONFIG_4KB_ROW = 0x00000002,
+};
+
+/**
+****************************************************************************************************
+* @brief Enums that define bank interleave size config
+****************************************************************************************************
+*/
+enum BankInterleaveSizeConfig
+{
+ ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x00000000,
+ ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x00000001,
+ ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x00000002,
+ ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x00000003,
+};
+
+/**
+****************************************************************************************************
+* @brief Enums that define engine tile size config
+****************************************************************************************************
+*/
+enum ShaderEngineTileSizeConfig
+{
+ ADDR_CONFIG_SE_TILE_16 = 0x00000000,
+ ADDR_CONFIG_SE_TILE_32 = 0x00000001,
+};
/**
-***************************************************************************************************
+****************************************************************************************************
* @brief This class contains asic independent address lib functionalities
-***************************************************************************************************
+****************************************************************************************************
*/
-class AddrLib : public AddrObject
+class Lib : public Object
{
public:
- virtual ~AddrLib();
+ virtual ~Lib();
static ADDR_E_RETURNCODE Create(
const ADDR_CREATE_INPUT* pCreateInfo, ADDR_CREATE_OUTPUT* pCreateOut);
delete this;
}
- static AddrLib* GetAddrLib(ADDR_HANDLE hLib);
+ static Lib* GetLib(ADDR_HANDLE hLib);
/// Returns AddrLib version (from compiled binary instead include file)
UINT_32 GetVersion()
}
/// Returns asic chip family name defined by AddrLib
- AddrChipFamily GetAddrChipFamily()
+ ChipFamily GetChipFamily()
{
return m_chipFamily;
}
BOOL_32 GetExportNorm(const ELEM_GETEXPORTNORM_INPUT* pIn) const;
- ADDR_E_RETURNCODE GetMaxAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const;
+ ADDR_E_RETURNCODE GetMaxAlignments(ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) const;
protected:
- AddrLib(); // Constructor is protected
- AddrLib(const AddrClient* pClient);
+ Lib(); // Constructor is protected
+ Lib(const Client* pClient);
/// Pure virtual function to get max alignments
- virtual ADDR_E_RETURNCODE HwlGetMaxAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const = 0;
+ virtual ADDR_E_RETURNCODE HwlGetMaxAlignments(ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) const = 0;
//
// Initialization
virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn) = 0;
/// Pure Virtual function for Hwl converting chip family
- virtual AddrChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision) = 0;
+ virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision) = 0;
/// Get equation table pointer and number of equations
virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const
//
// Misc helper
//
- static UINT_32 Bits2Number(UINT_32 bitNum,...);
+ static UINT_32 Bits2Number(UINT_32 bitNum, ...);
static UINT_32 GetNumFragments(UINT_32 numSamples, UINT_32 numFrags)
{
return (numFrags != 0) ? numFrags : Max(1u, numSamples);
}
- /// Returns pointer of AddrElemLib
- AddrElemLib* GetElemLib() const
+ /// Returns pointer of ElemLib
+ ElemLib* GetElemLib() const
{
return m_pElemLib;
}
private:
// Disallow the copy constructor
- AddrLib(const AddrLib& a);
+ Lib(const Lib& a);
// Disallow the assignment operator
- AddrLib& operator=(const AddrLib& a);
+ Lib& operator=(const Lib& a);
- VOID SetAddrChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision);
+ VOID SetChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision);
VOID SetMinPitchAlignPixels(UINT_32 minPitchAlignPixels);
protected:
- AddrLibClass m_class; ///< Store class type (HWL type)
+ LibClass m_class; ///< Store class type (HWL type)
- AddrChipFamily m_chipFamily; ///< Chip family translated from the one in atiid.h
+ ChipFamily m_chipFamily; ///< Chip family translated from the one in atiid.h
- UINT_32 m_chipRevision; ///< Revision id from xxx_id.h
+ UINT_32 m_chipRevision; ///< Revision id from xxx_id.h
- UINT_32 m_version; ///< Current version
+ UINT_32 m_version; ///< Current version
//
// Global parameters
//
- ADDR_CONFIG_FLAGS m_configFlags; ///< Global configuration flags. Note this is setup by
+ ConfigFlags m_configFlags; ///< Global configuration flags. Note this is setup by
/// AddrLib instead of Client except forceLinearAligned
- UINT_32 m_pipes; ///< Number of pipes
- UINT_32 m_banks; ///< Number of banks
+ UINT_32 m_pipes; ///< Number of pipes
+ UINT_32 m_banks; ///< Number of banks
/// For r800 this is MC_ARB_RAMCFG.NOOFBANK
/// Keep it here to do default parameter calculation
- UINT_32 m_pipeInterleaveBytes;
+ UINT_32 m_pipeInterleaveBytes;
///< Specifies the size of contiguous address space
/// within each tiling pipe when making linear
/// accesses. (Formerly Group Size)
- UINT_32 m_rowSize; ///< DRAM row size, in bytes
+ UINT_32 m_rowSize; ///< DRAM row size, in bytes
- UINT_32 m_minPitchAlignPixels; ///< Minimum pitch alignment in pixels
- UINT_32 m_maxSamples; ///< Max numSamples
+ UINT_32 m_minPitchAlignPixels; ///< Minimum pitch alignment in pixels
+ UINT_32 m_maxSamples; ///< Max numSamples
private:
- AddrElemLib* m_pElemLib; ///< Element Lib pointer
+ ElemLib* m_pElemLib; ///< Element Lib pointer
};
-AddrLib* AddrSIHwlInit (const AddrClient* pClient);
-AddrLib* AddrCIHwlInit (const AddrClient* pClient);
+Lib* SiHwlInit (const Client* pClient);
+Lib* CiHwlInit (const Client* pClient);
+Lib* Gfx9HwlInit (const Client* pClient);
-#endif
+} // Addr
+#endif
projects / mesa.git / blobdiff