nir: Handle all array stride cases in nir_deref_instr_array_stride

[mesa.git] / src / amd / common / ac_binary.c

diff --git a/src/amd/common/ac_binary.c b/src/amd/common/ac_binary.c
index 652ff228032050c2e7ca561f010b4ddbdd81ce86..4651c064abd5731f807f8af08ecf243226790da6 100644 (file)
--- a/src/amd/common/ac_binary.c
+++ b/src/amd/common/ac_binary.c
@@ -21,6 +21,7 @@
  * SOFTWARE.
  */
 
+#include "ac_gpu_info.h"
 #include "ac_binary.h"
 
 #include "util/u_math.h"
@@ -37,10 +38,12 @@
 
 /* Parse configuration data in .AMDGPU.config section format. */
 void ac_parse_shader_binary_config(const char *data, size_t nbytes,
+                                  unsigned wave_size,
                                   bool really_needs_scratch,
+                                  const struct radeon_info *info,
                                   struct ac_shader_config *conf)
 {
-       uint32_t wavesize = 0;
+       uint32_t scratch_size = 0;
 
        for (size_t i = 0; i < nbytes; i += 8) {
                unsigned reg = util_le32_to_cpu(*(uint32_t*)(data + i));
@@ -51,18 +54,42 @@ void ac_parse_shader_binary_config(const char *data, size_t nbytes,
                case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
                case R_00B848_COMPUTE_PGM_RSRC1:
                case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
+                       if (wave_size == 32)
+                               conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 8);
+                       else
+                               conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
+
                        conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
-                       conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
+                       /* TODO: LLVM doesn't set FLOAT_MODE for non-compute shaders */
                        conf->float_mode =  G_00B028_FLOAT_MODE(value);
                        conf->rsrc1 = value;
                        break;
                case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
                        conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
+                       /* TODO: LLVM doesn't set SHARED_VGPR_CNT for all shader types */
+                       conf->num_shared_vgprs = G_00B02C_SHARED_VGPR_CNT(value);
+                       conf->rsrc2 = value;
+                       break;
+               case R_00B12C_SPI_SHADER_PGM_RSRC2_VS:
+                       conf->num_shared_vgprs = G_00B12C_SHARED_VGPR_CNT(value);
+                       conf->rsrc2 = value;
+                       break;
+               case R_00B22C_SPI_SHADER_PGM_RSRC2_GS:
+                       conf->num_shared_vgprs = G_00B22C_SHARED_VGPR_CNT(value);
+                       conf->rsrc2 = value;
+                       break;
+               case R_00B42C_SPI_SHADER_PGM_RSRC2_HS:
+                       conf->num_shared_vgprs = G_00B42C_SHARED_VGPR_CNT(value);
+                       conf->rsrc2 = value;
                        break;
                case R_00B84C_COMPUTE_PGM_RSRC2:
                        conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
                        conf->rsrc2 = value;
                        break;
+               case R_00B8A0_COMPUTE_PGM_RSRC3:
+                       conf->num_shared_vgprs = G_00B8A0_SHARED_VGPR_CNT(value);
+                       conf->rsrc3 = value;
+                       break;
                case R_0286CC_SPI_PS_INPUT_ENA:
                        conf->spi_ps_input_ena = value;
                        break;
@@ -72,7 +99,7 @@ void ac_parse_shader_binary_config(const char *data, size_t nbytes,
                case R_0286E8_SPI_TMPRING_SIZE:
                case R_00B860_COMPUTE_TMPRING_SIZE:
                        /* WAVESIZE is in units of 256 dwords. */
-                       wavesize = value;
+                       scratch_size = value;
                        break;
                case SPILLED_SGPRS:
                        conf->spilled_sgprs = value;
@@ -99,6 +126,27 @@ void ac_parse_shader_binary_config(const char *data, size_t nbytes,
 
        if (really_needs_scratch) {
                /* sgprs spills aren't spilling */
-               conf->scratch_bytes_per_wave = G_00B860_WAVESIZE(wavesize) * 256 * 4;
+               conf->scratch_bytes_per_wave = G_00B860_WAVESIZE(scratch_size) * 256 * 4;
        }
+
+       /* GFX 10.3 internally:
+        * - aligns VGPRS to 16 for Wave32 and 8 for Wave64
+        * - aligns LDS to 1024
+        *
+        * For shader-db stats, set num_vgprs that the hw actually uses.
+        */
+       if (info->chip_class >= GFX10_3) {
+               conf->num_vgprs = align(conf->num_vgprs, wave_size == 32 ? 16 : 8);
+       }
+
+       /* Enable 64-bit and 16-bit denormals, because there is no performance
+        * cost.
+        *
+        * Don't enable denormals for 32-bit floats, because:
+        * - denormals disable output modifiers
+        * - denormals break v_mad_f32
+        * - GFX6 & GFX7 would be very slow
+        */
+       conf->float_mode &= ~V_00B028_FP_ALL_DENORMS;
+       conf->float_mode |= V_00B028_FP_64_DENORMS;
 }