ac: add more fields to ac_gpu_info

[mesa.git] / src / amd / common / ac_binary.c

diff --git a/src/amd/common/ac_binary.c b/src/amd/common/ac_binary.c
index 652ff228032050c2e7ca561f010b4ddbdd81ce86..5f92a57d7bf9c06b0b74203c7f673e676c03984c 100644 (file)
--- a/src/amd/common/ac_binary.c
+++ b/src/amd/common/ac_binary.c
@@ -37,10 +37,11 @@
 
 /* Parse configuration data in .AMDGPU.config section format. */
 void ac_parse_shader_binary_config(const char *data, size_t nbytes,
+                                  unsigned wave_size,
                                   bool really_needs_scratch,
                                   struct ac_shader_config *conf)
 {
-       uint32_t wavesize = 0;
+       uint32_t scratch_size = 0;
 
        for (size_t i = 0; i < nbytes; i += 8) {
                unsigned reg = util_le32_to_cpu(*(uint32_t*)(data + i));
@@ -51,18 +52,40 @@ void ac_parse_shader_binary_config(const char *data, size_t nbytes,
                case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
                case R_00B848_COMPUTE_PGM_RSRC1:
                case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
+                       if (wave_size == 32)
+                               conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 8);
+                       else
+                               conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
+
                        conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
-                       conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
                        conf->float_mode =  G_00B028_FLOAT_MODE(value);
                        conf->rsrc1 = value;
                        break;
                case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
                        conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
+                       conf->num_shared_vgprs = G_00B02C_SHARED_VGPR_CNT(value);
+                       conf->rsrc2 = value;
+                       break;
+               case R_00B12C_SPI_SHADER_PGM_RSRC2_VS:
+                       conf->num_shared_vgprs = G_00B12C_SHARED_VGPR_CNT(value);
+                       conf->rsrc2 = value;
+                       break;
+               case R_00B22C_SPI_SHADER_PGM_RSRC2_GS:
+                       conf->num_shared_vgprs = G_00B22C_SHARED_VGPR_CNT(value);
+                       conf->rsrc2 = value;
+                       break;
+               case R_00B42C_SPI_SHADER_PGM_RSRC2_HS:
+                       conf->num_shared_vgprs = G_00B42C_SHARED_VGPR_CNT(value);
+                       conf->rsrc2 = value;
                        break;
                case R_00B84C_COMPUTE_PGM_RSRC2:
                        conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
                        conf->rsrc2 = value;
                        break;
+               case R_00B8A0_COMPUTE_PGM_RSRC3:
+                       conf->num_shared_vgprs = G_00B8A0_SHARED_VGPR_CNT(value);
+                       conf->rsrc3 = value;
+                       break;
                case R_0286CC_SPI_PS_INPUT_ENA:
                        conf->spi_ps_input_ena = value;
                        break;
@@ -72,7 +95,7 @@ void ac_parse_shader_binary_config(const char *data, size_t nbytes,
                case R_0286E8_SPI_TMPRING_SIZE:
                case R_00B860_COMPUTE_TMPRING_SIZE:
                        /* WAVESIZE is in units of 256 dwords. */
-                       wavesize = value;
+                       scratch_size = value;
                        break;
                case SPILLED_SGPRS:
                        conf->spilled_sgprs = value;
@@ -99,6 +122,6 @@ void ac_parse_shader_binary_config(const char *data, size_t nbytes,
 
        if (really_needs_scratch) {
                /* sgprs spills aren't spilling */
-               conf->scratch_bytes_per_wave = G_00B860_WAVESIZE(wavesize) * 256 * 4;
+               conf->scratch_bytes_per_wave = G_00B860_WAVESIZE(scratch_size) * 256 * 4;
        }
 }