#include "ac_gpu_info.h"
#include "sid.h"
-#include "gfx9d.h"
#include "util/u_math.h"
case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
return 16;
default:
- fprintf(stderr, "Invalid CIK pipe configuration, assuming P2\n");
+ fprintf(stderr, "Invalid GFX7 pipe configuration, assuming P2\n");
assert(!"this should never occur");
return 2;
}
info->pci_func = devinfo->businfo.pci->func;
drmFreeDevice(&devinfo);
+ assert(info->drm_major == 3);
+ info->is_amdgpu = true;
+
/* Query hardware and driver information. */
r = amdgpu_query_gpu_info(dev, amdinfo);
if (r) {
return false;
}
- if (info->drm_major == 3 && info->drm_minor >= 17) {
+ if (info->drm_minor >= 17) {
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
}
}
- if (info->drm_major == 3 && info->drm_minor >= 17) {
+ if (info->drm_minor >= 17) {
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
}
}
- if (info->drm_major == 3 && info->drm_minor >= 17) {
+ if (info->drm_minor >= 17) {
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_ENC, 0, &vcn_enc);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
}
}
- if (info->drm_major == 3 && info->drm_minor >= 27) {
+ if (info->drm_minor >= 27) {
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0, &vcn_jpeg);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
if (info->family >= CHIP_VEGA10)
info->chip_class = GFX9;
else if (info->family >= CHIP_TONGA)
- info->chip_class = VI;
+ info->chip_class = GFX8;
else if (info->family >= CHIP_BONAIRE)
- info->chip_class = CIK;
+ info->chip_class = GFX7;
else if (info->family >= CHIP_TAHITI)
- info->chip_class = SI;
+ info->chip_class = GFX6;
else {
fprintf(stderr, "amdgpu: Unknown family.\n");
return false;
}
+ info->marketing_name = amdgpu_get_marketing_name(dev);
+ info->is_pro_graphics = info->marketing_name &&
+ (!strcmp(info->marketing_name, "Pro") ||
+ !strcmp(info->marketing_name, "PRO") ||
+ !strcmp(info->marketing_name, "Frontier"));
+
/* Set which chips have dedicated VRAM. */
info->has_dedicated_vram =
!(amdinfo->ids_flags & AMDGPU_IDS_FLAGS_FUSION);
info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
info->has_ctx_priority = info->drm_minor >= 22;
- /* TODO: Enable this once the kernel handles it efficiently. */
- info->has_local_buffers = info->drm_minor >= 20 &&
- !info->has_dedicated_vram;
+ info->has_local_buffers = info->drm_minor >= 20;
info->kernel_flushes_hdp_before_ib = true;
info->htile_cmask_support_1d_tiling = true;
info->si_TA_CS_BC_BASE_ADDR_allowed = true;
info->has_bo_metadata = true;
info->has_gpu_reset_status_query = true;
- info->has_gpu_reset_counter_query = false;
info->has_eqaa_surface_allocator = true;
info->has_format_bc1_through_bc7 = true;
- /* DRM 3.1.0 doesn't flush TC for VI correctly. */
- info->kernel_flushes_tc_l2_after_ib = info->chip_class != VI ||
+ /* DRM 3.1.0 doesn't flush TC for GFX8 correctly. */
+ info->kernel_flushes_tc_l2_after_ib = info->chip_class != GFX8 ||
info->drm_minor >= 2;
info->has_indirect_compute_dispatch = true;
- /* SI doesn't support unaligned loads. */
- info->has_unaligned_shader_loads = info->chip_class != SI;
- /* Disable sparse mappings on SI due to VM faults in CP DMA. Enable them once
+ /* GFX6 doesn't support unaligned loads. */
+ info->has_unaligned_shader_loads = info->chip_class != GFX6;
+ /* Disable sparse mappings on GFX6 due to VM faults in CP DMA. Enable them once
* these faults are mitigated in software.
* Disable sparse mappings on GFX9 due to hangs.
*/
info->has_sparse_vm_mappings =
- info->chip_class >= CIK && info->chip_class <= VI &&
+ info->chip_class >= GFX7 && info->chip_class <= GFX8 &&
info->drm_minor >= 13;
info->has_2d_tiling = true;
info->has_read_registers_query = true;
+ info->has_scheduled_fence_dependency = info->drm_minor >= 28;
info->num_render_backends = amdinfo->rb_pipes;
/* The value returned by the kernel driver was wrong. */
info->pte_fragment_size = alignment_info.size_local;
info->gart_page_size = alignment_info.size_remote;
- if (info->chip_class == SI)
+ if (info->chip_class == GFX6)
info->gfx_ib_pad_with_type2 = TRUE;
unsigned ib_align = 0;
assert(ib_align);
info->ib_start_alignment = ib_align;
+ if (info->drm_minor >= 31 &&
+ (info->family == CHIP_RAVEN ||
+ info->family == CHIP_RAVEN2)) {
+ if (info->num_render_backends == 1)
+ info->use_display_dcc_unaligned = true;
+ else
+ info->use_display_dcc_with_retile_blit = true;
+ }
+
+ info->has_gds_ordered_append = info->chip_class >= GFX7 &&
+ info->drm_minor >= 29 &&
+ HAVE_LLVM >= 0x0800;
return true;
}
printf(" clock_crystal_freq = %i\n", info->clock_crystal_freq);
printf(" tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
+ printf(" use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned);
+ printf(" use_display_dcc_with_retile_blit = %u\n", info->use_display_dcc_with_retile_blit);
+
printf("Memory info:\n");
printf(" pte_fragment_size = %u\n", info->pte_fragment_size);
printf(" gart_page_size = %u\n", info->gart_page_size);
printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
printf(" has_bo_metadata = %u\n", info->has_bo_metadata);
printf(" has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
- printf(" has_gpu_reset_counter_query = %u\n", info->has_gpu_reset_counter_query);
printf(" has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
printf(" has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
printf(" kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
printf(" has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
printf(" has_2d_tiling = %u\n", info->has_2d_tiling);
printf(" has_read_registers_query = %u\n", info->has_read_registers_query);
+ printf(" has_gds_ordered_append = %u\n", info->has_gds_ordered_append);
+ printf(" has_scheduled_fence_dependency = %u\n", info->has_scheduled_fence_dependency);
printf("Shader core info:\n");
printf(" max_shader_clock = %i\n", info->max_shader_clock);
case CHIP_HAINAN:
case CHIP_KAVERI:
case CHIP_KABINI:
- case CHIP_MULLINS:
case CHIP_ICELAND:
case CHIP_CARRIZO:
case CHIP_STONEY:
/* 1 SE / 1 RB */
case CHIP_HAINAN:
case CHIP_KABINI:
- case CHIP_MULLINS:
case CHIP_STONEY:
raster_config = 0x00000000;
raster_config_1 = 0x00000000;
/* drm/radeon on Kaveri is buggy, so disable 1 RB to work around it.
* This decreases performance by up to 50% when the RB is the bottleneck.
*/
- if (info->family == CHIP_KAVERI && info->drm_major == 2)
+ if (info->family == CHIP_KAVERI && !info->is_amdgpu)
raster_config = 0x00000000;
/* Fiji: Old kernels have incorrect tiling config. This decreases
assert(rb_per_pkr == 1 || rb_per_pkr == 2);
- if (info->chip_class >= CIK) {
+ if (info->chip_class >= GFX7) {
unsigned raster_config_1 = *cik_raster_config_1_p;
if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
(!se_mask[2] && !se_mask[3]))) {
projects / mesa.git / blobdiff