amd: enable displayable DCC for everything newer than Navi1x

[mesa.git] / src / amd / common / ac_gpu_info.c

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 797de243b407eb2c481049cd09bd1bc1c90615c8..8c9e788ac6402aba4755fabb112d798e90cd55d1 100644 (file)
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -409,7 +409,8 @@ bool ac_query_gpu_info(int fd, void *dev_p,
                identify_chip(NAVI10);
                identify_chip(NAVI12);
                identify_chip(NAVI14);
-               identify_chip(SIENNA);
+               identify_chip(SIENNA_CICHLID);
+               identify_chip(NAVY_FLOUNDER);
                break;
        }
 
@@ -419,7 +420,7 @@ bool ac_query_gpu_info(int fd, void *dev_p,
                return false;
        }
 
-       if (info->family >= CHIP_SIENNA)
+       if (info->family >= CHIP_SIENNA_CICHLID)
                info->chip_class = GFX10_3;
        else if (info->family >= CHIP_NAVI10)
                info->chip_class = GFX10;
@@ -717,7 +718,8 @@ bool ac_query_gpu_info(int fd, void *dev_p,
               info->family == CHIP_RENOIR)) ||
             (info->drm_minor >= 34 &&
              (info->family == CHIP_NAVI12 ||
-              info->family == CHIP_NAVI14))) {
+              info->family == CHIP_NAVI14)) ||
+            info->chip_class >= GFX10_3) {
                if (info->num_render_backends == 1)
                        info->use_display_dcc_unaligned = true;
                else
@@ -741,7 +743,8 @@ bool ac_query_gpu_info(int fd, void *dev_p,
                case CHIP_RENOIR:
                case CHIP_NAVI10:
                case CHIP_NAVI12:
-               case CHIP_SIENNA:
+               case CHIP_SIENNA_CICHLID:
+               case CHIP_NAVY_FLOUNDER:
                        pc_lines = 1024;
                        break;
                case CHIP_NAVI14: