#include <stdio.h>
#include <xf86drm.h>
-#include <amdgpu_drm.h>
+#include "drm-uapi/amdgpu_drm.h"
#include <amdgpu.h>
return value ? true : false;
}
+static bool has_timeline_syncobj(int fd)
+{
+ uint64_t value;
+ if (drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &value))
+ return false;
+ return value ? true : false;
+}
+
static uint64_t fix_vram_size(uint64_t size)
{
/* The VRAM size is underreported, so we need to fix it, because
identify_chip(NAVI10);
identify_chip(NAVI12);
identify_chip(NAVI14);
+ identify_chip(SIENNA_CICHLID);
+ identify_chip(NAVY_FLOUNDER);
break;
}
return false;
}
- if (info->family >= CHIP_NAVI10)
+ if (info->family >= CHIP_SIENNA_CICHLID)
+ info->chip_class = GFX10_3;
+ else if (info->family >= CHIP_NAVI10)
info->chip_class = GFX10;
else if (info->family >= CHIP_VEGA10)
info->chip_class = GFX9;
uvd_enc.available_rings ? true : false;
info->has_userptr = true;
info->has_syncobj = has_syncobj(fd);
+ info->has_timeline_syncobj = has_timeline_syncobj(fd);
info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
info->has_ctx_priority = info->drm_minor >= 22;
info->has_unaligned_shader_loads = info->chip_class != GFX6;
/* Disable sparse mappings on GFX6 due to VM faults in CP DMA. Enable them once
* these faults are mitigated in software.
- * Disable sparse mappings on GFX9 due to hangs.
*/
- info->has_sparse_vm_mappings =
- info->chip_class >= GFX7 && info->chip_class <= GFX8 &&
- info->drm_minor >= 13;
+ info->has_sparse_vm_mappings = info->chip_class >= GFX7 && info->drm_minor >= 13;
info->has_2d_tiling = true;
info->has_read_registers_query = true;
info->has_scheduled_fence_dependency = info->drm_minor >= 28;
+ info->mid_command_buffer_preemption_enabled =
+ amdinfo->ids_flags & AMDGPU_IDS_FLAGS_PREEMPTION;
info->pa_sc_tile_steering_override = device_info.pa_sc_tile_steering_override;
info->num_render_backends = amdinfo->rb_pipes;
info->num_rings[RING_VCN_ENC] = util_bitcount(vcn_enc.available_rings);
info->num_rings[RING_VCN_JPEG] = util_bitcount(vcn_jpeg.available_rings);
+ /* This is "align_mask" copied from the kernel, maximums of all IP versions. */
+ info->ib_pad_dw_mask[RING_GFX] = 0xff;
+ info->ib_pad_dw_mask[RING_COMPUTE] = 0xff;
+ info->ib_pad_dw_mask[RING_DMA] = 0xf;
+ info->ib_pad_dw_mask[RING_UVD] = 0xf;
+ info->ib_pad_dw_mask[RING_VCE] = 0x3f;
+ info->ib_pad_dw_mask[RING_UVD_ENC] = 0x3f;
+ info->ib_pad_dw_mask[RING_VCN_DEC] = 0xf;
+ info->ib_pad_dw_mask[RING_VCN_ENC] = 0x3f;
+ info->ib_pad_dw_mask[RING_VCN_JPEG] = 0xf;
+
/* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
* on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
* SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.
info->family == CHIP_VEGA12 ||
info->family == CHIP_RAVEN ||
info->family == CHIP_RAVEN2 ||
- info->family == CHIP_RENOIR);
+ info->family == CHIP_RENOIR ||
+ info->chip_class >= GFX10_3);
info->has_out_of_order_rast = info->chip_class >= GFX8 &&
info->chip_class <= GFX9 &&
info->max_se >= 2;
/* Whether chips support double rate packed math instructions. */
- info->has_double_rate_fp16 = info->chip_class >= GFX9;
+ info->has_packed_math_16bit = info->chip_class >= GFX9;
/* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
info->has_load_ctx_reg_pkt = info->chip_class >= GFX9 ||
info->num_good_compute_units = 0;
for (i = 0; i < info->max_se; i++) {
for (j = 0; j < info->max_sh_per_se; j++) {
- info->cu_mask[i][j] = amdinfo->cu_bitmap[i][j];
+ /*
+ * The cu bitmap in amd gpu info structure is
+ * 4x4 size array, and it's usually suitable for Vega
+ * ASICs which has 4*2 SE/SH layout.
+ * But for Arcturus, SE/SH layout is changed to 8*1.
+ * To mostly reduce the impact, we make it compatible
+ * with current bitmap array as below:
+ * SE4,SH0 --> cu_bitmap[0][1]
+ * SE5,SH0 --> cu_bitmap[1][1]
+ * SE6,SH0 --> cu_bitmap[2][1]
+ * SE7,SH0 --> cu_bitmap[3][1]
+ */
+ info->cu_mask[i%4][j+i/4] = amdinfo->cu_bitmap[i%4][j+i/4];
info->num_good_compute_units +=
util_bitcount(info->cu_mask[i][j]);
}
}
- info->num_good_cu_per_sh = info->num_good_compute_units /
- (info->max_se * info->max_sh_per_se);
- /* Round down to the nearest multiple of 2, because the hw can't
- * disable CUs. It can only disable whole WGPs (dual-CUs).
+ /* On GFX10, only whole WGPs (in units of 2 CUs) can be disabled,
+ * and max - min <= 2.
*/
- if (info->chip_class >= GFX10)
- info->num_good_cu_per_sh -= info->num_good_cu_per_sh % 2;
+ unsigned cu_group = info->chip_class >= GFX10 ? 2 : 1;
+ info->max_good_cu_per_sa = DIV_ROUND_UP(info->num_good_compute_units,
+ (info->max_se * info->max_sh_per_se * cu_group)) * cu_group;
+ info->min_good_cu_per_sa = (info->num_good_compute_units /
+ (info->max_se * info->max_sh_per_se * cu_group)) * cu_group;
memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode,
sizeof(amdinfo->gb_tile_mode));
unsigned ib_align = 0;
ib_align = MAX2(ib_align, gfx.ib_start_alignment);
+ ib_align = MAX2(ib_align, gfx.ib_size_alignment);
ib_align = MAX2(ib_align, compute.ib_start_alignment);
+ ib_align = MAX2(ib_align, compute.ib_size_alignment);
ib_align = MAX2(ib_align, dma.ib_start_alignment);
+ ib_align = MAX2(ib_align, dma.ib_size_alignment);
ib_align = MAX2(ib_align, uvd.ib_start_alignment);
+ ib_align = MAX2(ib_align, uvd.ib_size_alignment);
ib_align = MAX2(ib_align, uvd_enc.ib_start_alignment);
+ ib_align = MAX2(ib_align, uvd_enc.ib_size_alignment);
ib_align = MAX2(ib_align, vce.ib_start_alignment);
+ ib_align = MAX2(ib_align, vce.ib_size_alignment);
ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
+ ib_align = MAX2(ib_align, vcn_dec.ib_size_alignment);
ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
+ ib_align = MAX2(ib_align, vcn_enc.ib_size_alignment);
ib_align = MAX2(ib_align, vcn_jpeg.ib_start_alignment);
- assert(ib_align);
- info->ib_start_alignment = ib_align;
-
- if (info->drm_minor >= 31 &&
- (info->family == CHIP_RAVEN ||
- info->family == CHIP_RAVEN2 ||
- info->family == CHIP_RENOIR)) {
+ ib_align = MAX2(ib_align, vcn_jpeg.ib_size_alignment);
+ /* GFX10 and maybe GFX9 need this alignment for cache coherency. */
+ if (info->chip_class >= GFX9)
+ ib_align = MAX2(ib_align, info->tcc_cache_line_size);
+ /* The kernel pads gfx and compute IBs to 256 dwords since:
+ * 66f3b2d527154bd258a57c8815004b5964aa1cf5
+ * Do the same.
+ */
+ ib_align = MAX2(ib_align, 1024);
+ info->ib_alignment = ib_align;
+
+ if ((info->drm_minor >= 31 &&
+ (info->family == CHIP_RAVEN ||
+ info->family == CHIP_RAVEN2 ||
+ info->family == CHIP_RENOIR)) ||
+ (info->drm_minor >= 34 &&
+ (info->family == CHIP_NAVI12 ||
+ info->family == CHIP_NAVI14)) ||
+ info->chip_class >= GFX10_3) {
if (info->num_render_backends == 1)
info->use_display_dcc_unaligned = true;
else
case CHIP_RENOIR:
case CHIP_NAVI10:
case CHIP_NAVI12:
+ case CHIP_SIENNA_CICHLID:
+ case CHIP_NAVY_FLOUNDER:
pc_lines = 1024;
break;
case CHIP_NAVI14:
if (info->chip_class >= GFX10)
info->num_sdp_interfaces = device_info.num_tcc_blocks;
- info->max_wave64_per_simd = info->family >= CHIP_POLARIS10 &&
- info->family <= CHIP_VEGAM ? 8 : 10;
+ if (info->chip_class >= GFX10_3)
+ info->max_wave64_per_simd = 16;
+ else if (info->chip_class == GFX10)
+ info->max_wave64_per_simd = 20;
+ else if (info->family >= CHIP_POLARIS10 && info->family <= CHIP_VEGAM)
+ info->max_wave64_per_simd = 8;
+ else
+ info->max_wave64_per_simd = 10;
- /* The number is per SIMD. There is enough SGPRs for the maximum number
- * of Wave32, which is double the number for Wave64.
- */
if (info->chip_class >= GFX10) {
- info->num_physical_sgprs_per_simd = 128 * info->max_wave64_per_simd * 2;
+ info->num_physical_sgprs_per_simd = 128 * info->max_wave64_per_simd;
info->min_sgpr_alloc = 128;
info->sgpr_alloc_granularity = 128;
/* Don't use late alloc on small chips. */
printf("CP info:\n");
printf(" gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
- printf(" ib_start_alignment = %u\n", info->ib_start_alignment);
+ printf(" ib_alignment = %u\n", info->ib_alignment);
printf(" me_fw_version = %i\n", info->me_fw_version);
printf(" me_fw_feature = %i\n", info->me_fw_feature);
printf(" pfp_fw_version = %i\n", info->pfp_fw_version);
printf(" has_userptr = %i\n", info->has_userptr);
printf(" has_syncobj = %u\n", info->has_syncobj);
printf(" has_syncobj_wait_for_submit = %u\n", info->has_syncobj_wait_for_submit);
+ printf(" has_timeline_syncobj = %u\n", info->has_timeline_syncobj);
printf(" has_fence_to_handle = %u\n", info->has_fence_to_handle);
printf(" has_ctx_priority = %u\n", info->has_ctx_priority);
printf(" has_local_buffers = %u\n", info->has_local_buffers);
printf(" has_read_registers_query = %u\n", info->has_read_registers_query);
printf(" has_gds_ordered_append = %u\n", info->has_gds_ordered_append);
printf(" has_scheduled_fence_dependency = %u\n", info->has_scheduled_fence_dependency);
+ printf(" mid_command_buffer_preemption_enabled = %u\n", info->mid_command_buffer_preemption_enabled);
printf("Shader core info:\n");
printf(" max_shader_clock = %i\n", info->max_shader_clock);
printf(" num_good_compute_units = %i\n", info->num_good_compute_units);
- printf(" num_good_cu_per_sh = %i\n", info->num_good_cu_per_sh);
+ printf(" max_good_cu_per_sa = %i\n", info->max_good_cu_per_sa);
+ printf(" min_good_cu_per_sa = %i\n", info->min_good_cu_per_sa);
printf(" max_se = %i\n", info->max_se);
printf(" max_sh_per_se = %i\n", info->max_sh_per_se);
printf(" max_wave64_per_simd = %i\n", info->max_wave64_per_simd);
projects / mesa.git / blobdiff