ac/nir: extract shader_info->fs.can_discard from NIR shader info

[mesa.git] / src / amd / common / ac_gpu_info.c

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 3dae2bd14c014f2fd0767f65a25cd116ff18cb58..929dfd2946ff4e27129a5794b88efdc3ed4b1fd1 100644 (file)
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -34,6 +34,8 @@
 #include <xf86drm.h>
 #include <amdgpu_drm.h>
 
+#include <amdgpu.h>
+
 #define CIK_TILE_MODE_COLOR_2D                 14
 
 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x)        (((x) >> 6) & 0x1f)
@@ -82,6 +84,14 @@ static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
    }
 }
 
+static bool has_syncobj(int fd)
+{
+       uint64_t value;
+       if (drmGetCap(fd, DRM_CAP_SYNCOBJ, &value))
+               return false;
+       return value ? true : false;
+}
+
 bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
                       struct radeon_info *info,
                       struct amdgpu_gpu_info *amdinfo)
@@ -249,14 +259,20 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
        info->max_shader_clock = amdinfo->max_engine_clk / 1000;
        info->max_se = amdinfo->num_shader_engines;
        info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
-       info->has_hw_decode = uvd.available_rings != 0;
+       info->has_hw_decode =
+               (uvd.available_rings != 0) || (vcn_dec.available_rings != 0);
        info->uvd_fw_version =
                uvd.available_rings ? uvd_version : 0;
        info->vce_fw_version =
                vce.available_rings ? vce_version : 0;
        info->has_userptr = true;
+       info->has_syncobj = has_syncobj(fd);
        info->num_render_backends = amdinfo->rb_pipes;
        info->clock_crystal_freq = amdinfo->gpu_counter_freq;
+       if (!info->clock_crystal_freq) {
+               fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
+               info->clock_crystal_freq = 1;
+       }
        info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */
        if (info->chip_class == GFX9) {
                info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);