ac: import ac_get_compute_resource_limits() from RadeonSI

[mesa.git] / src / amd / common / ac_gpu_info.c

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 596a9ebe5088b5e4a88b3a0f44d2e503bd54edf9..a501d840b25986aa4d3b251520ea855e6bc6003f 100644 (file)
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -895,3 +895,35 @@ ac_get_harvested_configs(struct radeon_info *info,
                }
        }
 }
+
+unsigned ac_get_compute_resource_limits(struct radeon_info *info,
+                                       unsigned waves_per_threadgroup,
+                                       unsigned max_waves_per_sh,
+                                       unsigned threadgroups_per_cu)
+{
+       unsigned compute_resource_limits =
+               S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
+
+       if (info->chip_class >= GFX7) {
+               unsigned num_cu_per_se = info->num_good_compute_units /
+                                        info->max_se;
+
+               /* Force even distribution on all SIMDs in CU if the workgroup
+                * size is 64. This has shown some good improvements if # of CUs
+                * per SE is not a multiple of 4.
+                */
+               if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
+                       compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
+
+               assert(threadgroups_per_cu >= 1 && threadgroups_per_cu <= 8);
+               compute_resource_limits |= S_00B854_WAVES_PER_SH(max_waves_per_sh) |
+                                          S_00B854_CU_GROUP_COUNT(threadgroups_per_cu - 1);
+       } else {
+               /* GFX6 */
+               if (max_waves_per_sh) {
+                       unsigned limit_div16 = DIV_ROUND_UP(max_waves_per_sh, 16);
+                       compute_resource_limits |= S_00B854_WAVES_PER_SH_SI(limit_div16);
+               }
+       }
+       return compute_resource_limits;
+}