#include "ac_gpu_info.h"
#include "sid.h"
+#include "util/macros.h"
#include "util/u_math.h"
#include <stdio.h>
return value ? true : false;
}
-bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
+bool ac_query_gpu_info(int fd, void *dev_p,
struct radeon_info *info,
struct amdgpu_gpu_info *amdinfo)
{
struct amdgpu_gds_resource_info gds = {};
uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
int r, i, j;
+ amdgpu_device_handle dev = dev_p;
drmDevicePtr devinfo;
/* Get PCI info. */
info->pci_func = devinfo->businfo.pci->func;
drmFreeDevice(&devinfo);
+ assert(info->drm_major == 3);
+ info->is_amdgpu = true;
+
/* Query hardware and driver information. */
r = amdgpu_query_gpu_info(dev, amdinfo);
if (r) {
return false;
}
- if (info->drm_major == 3 && info->drm_minor >= 17) {
+ if (info->drm_minor >= 17) {
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
}
}
- if (info->drm_major == 3 && info->drm_minor >= 17) {
+ if (info->drm_minor >= 17) {
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
}
}
- if (info->drm_major == 3 && info->drm_minor >= 17) {
+ if (info->drm_minor >= 17) {
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_ENC, 0, &vcn_enc);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
}
}
- if (info->drm_major == 3 && info->drm_minor >= 27) {
+ if (info->drm_minor >= 27) {
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0, &vcn_jpeg);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
info->name = "RAVEN2";
}
- if (info->family >= CHIP_VEGA10)
+ if (info->family >= CHIP_NAVI10)
+ info->chip_class = GFX10;
+ else if (info->family >= CHIP_VEGA10)
info->chip_class = GFX9;
else if (info->family >= CHIP_TONGA)
info->chip_class = GFX8;
return false;
}
+ info->family_id = amdinfo->family_id;
+ info->chip_external_rev = amdinfo->chip_external_rev;
info->marketing_name = amdgpu_get_marketing_name(dev);
info->is_pro_graphics = info->marketing_name &&
(!strcmp(info->marketing_name, "Pro") ||
info->has_read_registers_query = true;
info->has_scheduled_fence_dependency = info->drm_minor >= 28;
+ info->pa_sc_tile_steering_override = device_info.pa_sc_tile_steering_override;
info->num_render_backends = amdinfo->rb_pipes;
/* The value returned by the kernel driver was wrong. */
if (info->family == CHIP_KAVERI)
fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
info->clock_crystal_freq = 1;
}
- info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */
+ if (info->chip_class >= GFX10) {
+ info->tcc_cache_line_size = 128;
+ } else {
+ info->tcc_cache_line_size = 64;
+ }
info->gb_addr_config = amdinfo->gb_addr_cfg;
if (info->chip_class == GFX9) {
info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
assert(util_is_power_of_two_or_zero(dma.available_rings + 1));
assert(util_is_power_of_two_or_zero(compute.available_rings + 1));
+ info->has_graphics = gfx.available_rings > 0;
info->num_sdma_rings = util_bitcount(dma.available_rings);
info->num_compute_rings = util_bitcount(compute.available_rings);
+ /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
+ * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
+ * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.
+ */
+ info->has_clear_state = info->chip_class >= GFX7;
+
+ info->has_distributed_tess = info->chip_class >= GFX8 &&
+ info->max_se >= 2;
+
+ info->has_dcc_constant_encode = info->family == CHIP_RAVEN2 ||
+ info->family == CHIP_RENOIR ||
+ info->chip_class >= GFX10;
+
+ info->has_rbplus = info->family == CHIP_STONEY ||
+ info->chip_class >= GFX9;
+
+ info->has_out_of_order_rast = info->chip_class >= GFX8 &&
+ info->max_se >= 2;
+
+ /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
+ info->has_load_ctx_reg_pkt = info->chip_class >= GFX9 ||
+ (info->chip_class >= GFX8 &&
+ info->me_fw_feature >= 41);
+
+ info->cpdma_prefetch_writes_memory = info->chip_class <= GFX8;
+
/* Get the number of good compute units. */
info->num_good_compute_units = 0;
for (i = 0; i < info->max_se; i++)
info->gart_page_size = alignment_info.size_remote;
if (info->chip_class == GFX6)
- info->gfx_ib_pad_with_type2 = TRUE;
+ info->gfx_ib_pad_with_type2 = true;
unsigned ib_align = 0;
ib_align = MAX2(ib_align, gfx.ib_start_alignment);
if (info->drm_minor >= 31 &&
(info->family == CHIP_RAVEN ||
- info->family == CHIP_RAVEN2)) {
+ info->family == CHIP_RAVEN2 ||
+ info->family == CHIP_RENOIR)) {
if (info->num_render_backends == 1)
info->use_display_dcc_unaligned = true;
else
}
info->has_gds_ordered_append = info->chip_class >= GFX7 &&
- info->drm_minor >= 29 &&
- HAVE_LLVM >= 0x0800;
+ info->drm_minor >= 29;
return true;
}
printf(" pci_id = 0x%x\n", info->pci_id);
printf(" family = %i\n", info->family);
printf(" chip_class = %i\n", info->chip_class);
+ printf(" chip_external_rev = %i\n", info->chip_external_rev);
printf(" num_compute_rings = %u\n", info->num_compute_rings);
printf(" num_sdma_rings = %i\n", info->num_sdma_rings);
printf(" clock_crystal_freq = %i\n", info->clock_crystal_freq);
printf(" max_sh_per_se = %i\n", info->max_sh_per_se);
printf("Render backend info:\n");
+ printf(" pa_sc_tile_steering_override = 0x%x\n", info->pa_sc_tile_steering_override);
printf(" num_render_backends = %i\n", info->num_render_backends);
printf(" num_tile_pipes = %i\n", info->num_tile_pipes);
printf(" pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
/* drm/radeon on Kaveri is buggy, so disable 1 RB to work around it.
* This decreases performance by up to 50% when the RB is the bottleneck.
*/
- if (info->family == CHIP_KAVERI && info->drm_major == 2)
+ if (info->family == CHIP_KAVERI && !info->is_amdgpu)
raster_config = 0x00000000;
/* Fiji: Old kernels have incorrect tiling config. This decreases
}
}
}
+
+unsigned ac_get_compute_resource_limits(struct radeon_info *info,
+ unsigned waves_per_threadgroup,
+ unsigned max_waves_per_sh,
+ unsigned threadgroups_per_cu)
+{
+ unsigned compute_resource_limits =
+ S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
+
+ if (info->chip_class >= GFX7) {
+ unsigned num_cu_per_se = info->num_good_compute_units /
+ info->max_se;
+
+ /* Force even distribution on all SIMDs in CU if the workgroup
+ * size is 64. This has shown some good improvements if # of CUs
+ * per SE is not a multiple of 4.
+ */
+ if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
+ compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
+
+ assert(threadgroups_per_cu >= 1 && threadgroups_per_cu <= 8);
+ compute_resource_limits |= S_00B854_WAVES_PER_SH(max_waves_per_sh) |
+ S_00B854_CU_GROUP_COUNT(threadgroups_per_cu - 1);
+ } else {
+ /* GFX6 */
+ if (max_waves_per_sh) {
+ unsigned limit_div16 = DIV_ROUND_UP(max_waves_per_sh, 16);
+ compute_resource_limits |= S_00B854_WAVES_PER_SH_SI(limit_div16);
+ }
+ }
+ return compute_resource_limits;
+}