#include <xf86drm.h>
#include <amdgpu_drm.h>
+#include <amdgpu.h>
+
#define CIK_TILE_MODE_COLOR_2D 14
#define CIK__GB_TILE_MODE__PIPE_CONFIG(x) (((x) >> 6) & 0x1f)
}
}
+static bool has_syncobj(int fd)
+{
+ uint64_t value;
+ if (drmGetCap(fd, DRM_CAP_SYNCOBJ, &value))
+ return false;
+ return value ? true : false;
+}
+
bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
struct radeon_info *info,
struct amdgpu_gpu_info *amdinfo)
{
struct amdgpu_buffer_size_alignments alignment_info = {};
struct amdgpu_heap_info vram, vram_vis, gtt;
- struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, vce = {};
+ struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, vce = {}, vcn_dec = {}, vcn_enc = {};
uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
- uint32_t unused_feature;
int r, i, j;
drmDevicePtr devinfo;
return false;
}
+ if (info->drm_major == 3 && info->drm_minor >= 17) {
+ r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
+ if (r) {
+ fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
+ return false;
+ }
+ }
+
+ if (info->drm_major == 3 && info->drm_minor >= 17) {
+ r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_ENC, 0, &vcn_enc);
+ if (r) {
+ fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
+ return false;
+ }
+ }
+
r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
- &info->me_fw_version, &unused_feature);
+ &info->me_fw_version,
+ &info->me_fw_feature);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
return false;
}
r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0,
- &info->pfp_fw_version, &unused_feature);
+ &info->pfp_fw_version,
+ &info->pfp_fw_feature);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
return false;
}
r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_CE, 0, 0,
- &info->ce_fw_version, &unused_feature);
+ &info->ce_fw_version,
+ &info->ce_fw_feature);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
return false;
info->vce_harvest_config = amdinfo->vce_harvest_config;
switch (info->pci_id) {
-#define CHIPSET(pci_id, name, cfamily) case pci_id: info->family = CHIP_##cfamily; break;
+#define CHIPSET(pci_id, cfamily) case pci_id: info->family = CHIP_##cfamily; break;
#include "pci_ids/radeonsi_pci_ids.h"
#undef CHIPSET
info->max_shader_clock = amdinfo->max_engine_clk / 1000;
info->max_se = amdinfo->num_shader_engines;
info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
- info->has_hw_decode = uvd.available_rings != 0;
+ info->has_hw_decode =
+ (uvd.available_rings != 0) || (vcn_dec.available_rings != 0);
info->uvd_fw_version =
uvd.available_rings ? uvd_version : 0;
info->vce_fw_version =
vce.available_rings ? vce_version : 0;
info->has_userptr = true;
+ info->has_syncobj = has_syncobj(fd);
+ info->has_syncobj_wait = info->has_syncobj && info->drm_minor >= 20;
+ info->has_sync_file = info->has_syncobj && info->drm_minor >= 21;
+ info->has_ctx_priority = info->drm_minor >= 22;
info->num_render_backends = amdinfo->rb_pipes;
info->clock_crystal_freq = amdinfo->gpu_counter_freq;
+ if (!info->clock_crystal_freq) {
+ fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
+ info->clock_crystal_freq = 1;
+ }
info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */
if (info->chip_class == GFX9) {
info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
return true;
}
+void ac_compute_driver_uuid(char *uuid, size_t size)
+{
+ char amd_uuid[] = "AMD-MESA-DRV";
+
+ assert(size >= sizeof(amd_uuid));
+
+ memset(uuid, 0, size);
+ strncpy(uuid, amd_uuid, size);
+}
+
+void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size)
+{
+ uint32_t *uint_uuid = (uint32_t*)uuid;
+
+ assert(size >= sizeof(uint32_t)*4);
+
+ /**
+ * Use the device info directly instead of using a sha1. GL/VK UUIDs
+ * are 16 byte vs 20 byte for sha1, and the truncation that would be
+ * required would get rid of part of the little entropy we have.
+ * */
+ memset(uuid, 0, size);
+ uint_uuid[0] = info->pci_domain;
+ uint_uuid[1] = info->pci_bus;
+ uint_uuid[2] = info->pci_dev;
+ uint_uuid[3] = info->pci_func;
+}
+
+void ac_print_gpu_info(struct radeon_info *info)
+{
+ printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
+ info->pci_domain, info->pci_bus,
+ info->pci_dev, info->pci_func);
+ printf("pci_id = 0x%x\n", info->pci_id);
+ printf("family = %i\n", info->family);
+ printf("chip_class = %i\n", info->chip_class);
+ printf("pte_fragment_size = %u\n", info->pte_fragment_size);
+ printf("gart_page_size = %u\n", info->gart_page_size);
+ printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 1024*1024));
+ printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 1024*1024));
+ printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size, 1024*1024));
+ printf("max_alloc_size = %i MB\n",
+ (int)DIV_ROUND_UP(info->max_alloc_size, 1024*1024));
+ printf("min_alloc_size = %u\n", info->min_alloc_size);
+ printf("has_dedicated_vram = %u\n", info->has_dedicated_vram);
+ printf("has_virtual_memory = %i\n", info->has_virtual_memory);
+ printf("gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
+ printf("has_hw_decode = %u\n", info->has_hw_decode);
+ printf("num_sdma_rings = %i\n", info->num_sdma_rings);
+ printf("num_compute_rings = %u\n", info->num_compute_rings);
+ printf("uvd_fw_version = %u\n", info->uvd_fw_version);
+ printf("vce_fw_version = %u\n", info->vce_fw_version);
+ printf("me_fw_version = %i\n", info->me_fw_version);
+ printf("me_fw_feature = %i\n", info->me_fw_feature);
+ printf("pfp_fw_version = %i\n", info->pfp_fw_version);
+ printf("pfp_fw_feature = %i\n", info->pfp_fw_feature);
+ printf("ce_fw_version = %i\n", info->ce_fw_version);
+ printf("ce_fw_feature = %i\n", info->ce_fw_feature);
+ printf("vce_harvest_config = %i\n", info->vce_harvest_config);
+ printf("clock_crystal_freq = %i\n", info->clock_crystal_freq);
+ printf("tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
+ printf("drm = %i.%i.%i\n", info->drm_major,
+ info->drm_minor, info->drm_patchlevel);
+ printf("has_userptr = %i\n", info->has_userptr);
+ printf("has_syncobj = %u\n", info->has_syncobj);
+ printf("has_sync_file = %u\n", info->has_sync_file);
+
+ printf("r600_max_quad_pipes = %i\n", info->r600_max_quad_pipes);
+ printf("max_shader_clock = %i\n", info->max_shader_clock);
+ printf("num_good_compute_units = %i\n", info->num_good_compute_units);
+ printf("max_se = %i\n", info->max_se);
+ printf("max_sh_per_se = %i\n", info->max_sh_per_se);
+
+ printf("r600_gb_backend_map = %i\n", info->r600_gb_backend_map);
+ printf("r600_gb_backend_map_valid = %i\n", info->r600_gb_backend_map_valid);
+ printf("r600_num_banks = %i\n", info->r600_num_banks);
+ printf("num_render_backends = %i\n", info->num_render_backends);
+ printf("num_tile_pipes = %i\n", info->num_tile_pipes);
+ printf("pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
+ printf("enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
+ printf("max_alignment = %u\n", (unsigned)info->max_alignment);
+}
projects / mesa.git / blobdiff