radeonsi: lower IO intrinsics - complete rewrite of input/output scanning

[mesa.git] / src / amd / common / ac_gpu_info.c

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 797de243b407eb2c481049cd09bd1bc1c90615c8..e6ed816f74c4f58fb5a5427ce36f577bbb7f48fd 100644 (file)
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -409,7 +409,8 @@ bool ac_query_gpu_info(int fd, void *dev_p,
                identify_chip(NAVI10);
                identify_chip(NAVI12);
                identify_chip(NAVI14);
-               identify_chip(SIENNA);
+               identify_chip(SIENNA_CICHLID);
+               identify_chip(NAVY_FLOUNDER);
                break;
        }
 
@@ -419,7 +420,7 @@ bool ac_query_gpu_info(int fd, void *dev_p,
                return false;
        }
 
-       if (info->family >= CHIP_SIENNA)
+       if (info->family >= CHIP_SIENNA_CICHLID)
                info->chip_class = GFX10_3;
        else if (info->family >= CHIP_NAVI10)
                info->chip_class = GFX10;
@@ -539,7 +540,7 @@ bool ac_query_gpu_info(int fd, void *dev_p,
                info->tcc_cache_line_size = 64;
        }
        info->gb_addr_config = amdinfo->gb_addr_cfg;
-       if (info->chip_class == GFX9) {
+       if (info->chip_class >= GFX9) {
                info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
                info->pipe_interleave_bytes =
                        256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo->gb_addr_cfg);
@@ -717,7 +718,8 @@ bool ac_query_gpu_info(int fd, void *dev_p,
               info->family == CHIP_RENOIR)) ||
             (info->drm_minor >= 34 &&
              (info->family == CHIP_NAVI12 ||
-              info->family == CHIP_NAVI14))) {
+              info->family == CHIP_NAVI14)) ||
+            info->chip_class >= GFX10_3) {
                if (info->num_render_backends == 1)
                        info->use_display_dcc_unaligned = true;
                else
@@ -741,7 +743,8 @@ bool ac_query_gpu_info(int fd, void *dev_p,
                case CHIP_RENOIR:
                case CHIP_NAVI10:
                case CHIP_NAVI12:
-               case CHIP_SIENNA:
+               case CHIP_SIENNA_CICHLID:
+               case CHIP_NAVY_FLOUNDER:
                        pc_lines = 1024;
                        break;
                case CHIP_NAVI14:
@@ -1302,7 +1305,7 @@ unsigned ac_get_compute_resource_limits(struct radeon_info *info,
                /* GFX6 */
                if (max_waves_per_sh) {
                        unsigned limit_div16 = DIV_ROUND_UP(max_waves_per_sh, 16);
-                       compute_resource_limits |= S_00B854_WAVES_PER_SH_SI(limit_div16);
+                       compute_resource_limits |= S_00B854_WAVES_PER_SH_GFX6(limit_div16);
                }
        }
        return compute_resource_limits;