ac: add has_load_ctx_reg_pkt to ac_gpu_info

[mesa.git] / src / amd / common / ac_gpu_info.h

diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index a897496da487153b4a08ad4476bebd68bfc9ede2..10a3205f44d9b4acdfd374ffa2e1d625babe71ca 100644 (file)
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -35,8 +35,6 @@
 extern "C" {
 #endif
 
-/* Prior to C11 the following may trigger a typedef redeclaration warning */
-typedef struct amdgpu_device *amdgpu_device_handle;
 struct amdgpu_gpu_info;
 
 struct radeon_info {
@@ -48,13 +46,29 @@ struct radeon_info {
 
        /* Device info. */
        const char                  *name;
+       const char                  *marketing_name;
+       bool                        is_pro_graphics;
        uint32_t                    pci_id;
        enum radeon_family          family;
        enum chip_class             chip_class;
+       uint32_t                    family_id;
+       uint32_t                    chip_external_rev;
+       bool                        has_graphics; /* false if the chip is compute-only */
        uint32_t                    num_compute_rings;
        uint32_t                    num_sdma_rings;
        uint32_t                    clock_crystal_freq;
        uint32_t                    tcc_cache_line_size;
+       bool                        has_clear_state;
+       bool                        has_distributed_tess;
+       bool                        has_dcc_constant_encode;
+       bool                        has_rbplus; /* if RB+ registers exist */
+       bool                        has_load_ctx_reg_pkt;
+
+       /* There are 2 display DCC codepaths, because display expects unaligned DCC. */
+       /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */
+       bool                        use_display_dcc_unaligned;
+       /* Allocate both aligned and unaligned DCC and use the retile blit. */
+       bool                        use_display_dcc_with_retile_blit;
 
        /* Memory info. */
        uint32_t                    pte_fragment_size;
@@ -91,6 +105,7 @@ struct radeon_info {
        uint32_t                    drm_major; /* version */
        uint32_t                    drm_minor;
        uint32_t                    drm_patchlevel;
+       bool                        is_amdgpu;
        bool                        has_userptr;
        bool                        has_syncobj;
        bool                        has_syncobj_wait_for_submit;
@@ -102,7 +117,6 @@ struct radeon_info {
        bool                        si_TA_CS_BC_BASE_ADDR_allowed;
        bool                        has_bo_metadata;
        bool                        has_gpu_reset_status_query;
-       bool                        has_gpu_reset_counter_query;
        bool                        has_eqaa_surface_allocator;
        bool                        has_format_bc1_through_bc7;
        bool                        kernel_flushes_tc_l2_after_ib;
@@ -111,11 +125,14 @@ struct radeon_info {
        bool                        has_sparse_vm_mappings;
        bool                        has_2d_tiling;
        bool                        has_read_registers_query;
+       bool                        has_gds_ordered_append;
+       bool                        has_scheduled_fence_dependency;
 
        /* Shader cores. */
        uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
        uint32_t                    max_shader_clock;
        uint32_t                    num_good_compute_units;
+       uint32_t                    num_good_cu_per_sh;
        uint32_t                    num_tcc_blocks;
        uint32_t                    max_se; /* shader engines */
        uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
@@ -127,6 +144,7 @@ struct radeon_info {
        bool                        r600_gb_backend_map_valid;
        uint32_t                    r600_num_banks;
        uint32_t                    gb_addr_config;
+       uint32_t                    pa_sc_tile_steering_override; /* CLEAR_STATE also sets this */
        uint32_t                    num_render_backends;
        uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
        uint32_t                    pipe_interleave_bytes;
@@ -138,7 +156,7 @@ struct radeon_info {
        uint32_t                    cik_macrotile_mode_array[16];
 };
 
-bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
+bool ac_query_gpu_info(int fd, void *dev_p,
                       struct radeon_info *info,
                       struct amdgpu_gpu_info *amdinfo);
 
@@ -149,11 +167,16 @@ void ac_print_gpu_info(struct radeon_info *info);
 int ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family);
 void ac_get_raster_config(struct radeon_info *info,
                          uint32_t *raster_config_p,
-                         uint32_t *raster_config_1_p);
+                         uint32_t *raster_config_1_p,
+                         uint32_t *se_tile_repeat_p);
 void ac_get_harvested_configs(struct radeon_info *info,
                              unsigned raster_config,
                              unsigned *cik_raster_config_1_p,
                              unsigned *raster_config_se);
+unsigned ac_get_compute_resource_limits(struct radeon_info *info,
+                                       unsigned waves_per_threadgroup,
+                                       unsigned max_waves_per_sh,
+                                       unsigned threadgroups_per_cu);
 
 static inline unsigned ac_get_max_simd_waves(enum radeon_family family)
 {
@@ -170,6 +193,12 @@ static inline unsigned ac_get_max_simd_waves(enum radeon_family family)
        }
 }
 
+static inline uint32_t
+ac_get_num_physical_sgprs(enum chip_class chip_class)
+{
+       return chip_class >= GFX8 ? 800 : 512;
+}
+
 #ifdef __cplusplus
 }
 #endif