ac: add has_load_ctx_reg_pkt to ac_gpu_info

[mesa.git] / src / amd / common / ac_gpu_info.h

diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index cea6181dc7ecd145b704112bca4f37aeed05baed..10a3205f44d9b4acdfd374ffa2e1d625babe71ca 100644 (file)
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -53,10 +53,16 @@ struct radeon_info {
        enum chip_class             chip_class;
        uint32_t                    family_id;
        uint32_t                    chip_external_rev;
+       bool                        has_graphics; /* false if the chip is compute-only */
        uint32_t                    num_compute_rings;
        uint32_t                    num_sdma_rings;
        uint32_t                    clock_crystal_freq;
        uint32_t                    tcc_cache_line_size;
+       bool                        has_clear_state;
+       bool                        has_distributed_tess;
+       bool                        has_dcc_constant_encode;
+       bool                        has_rbplus; /* if RB+ registers exist */
+       bool                        has_load_ctx_reg_pkt;
 
        /* There are 2 display DCC codepaths, because display expects unaligned DCC. */
        /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */
@@ -138,6 +144,7 @@ struct radeon_info {
        bool                        r600_gb_backend_map_valid;
        uint32_t                    r600_num_banks;
        uint32_t                    gb_addr_config;
+       uint32_t                    pa_sc_tile_steering_override; /* CLEAR_STATE also sets this */
        uint32_t                    num_render_backends;
        uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
        uint32_t                    pipe_interleave_bytes;
@@ -166,6 +173,10 @@ void ac_get_harvested_configs(struct radeon_info *info,
                              unsigned raster_config,
                              unsigned *cik_raster_config_1_p,
                              unsigned *raster_config_se);
+unsigned ac_get_compute_resource_limits(struct radeon_info *info,
+                                       unsigned waves_per_threadgroup,
+                                       unsigned max_waves_per_sh,
+                                       unsigned threadgroups_per_cu);
 
 static inline unsigned ac_get_max_simd_waves(enum radeon_family family)
 {