ac: move PBB MAX_ALLOC_COUNT into radeon_info

[mesa.git] / src / amd / common / ac_gpu_info.h

diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index cea6181dc7ecd145b704112bca4f37aeed05baed..555f7175e87ed145dfebde6e309a67d263018bb2 100644 (file)
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -53,10 +53,20 @@ struct radeon_info {
        enum chip_class             chip_class;
        uint32_t                    family_id;
        uint32_t                    chip_external_rev;
+       bool                        has_graphics; /* false if the chip is compute-only */
        uint32_t                    num_compute_rings;
        uint32_t                    num_sdma_rings;
        uint32_t                    clock_crystal_freq;
        uint32_t                    tcc_cache_line_size;
+       bool                        has_clear_state;
+       bool                        has_distributed_tess;
+       bool                        has_dcc_constant_encode;
+       bool                        has_rbplus; /* if RB+ registers exist */
+       bool                        rbplus_allowed; /* if RB+ is allowed */
+       bool                        has_load_ctx_reg_pkt;
+       bool                        has_out_of_order_rast;
+       bool                        cpdma_prefetch_writes_memory;
+       uint32_t                    pbb_max_alloc_count;
 
        /* There are 2 display DCC codepaths, because display expects unaligned DCC. */
        /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */
@@ -138,6 +148,7 @@ struct radeon_info {
        bool                        r600_gb_backend_map_valid;
        uint32_t                    r600_num_banks;
        uint32_t                    gb_addr_config;
+       uint32_t                    pa_sc_tile_steering_override; /* CLEAR_STATE also sets this */
        uint32_t                    num_render_backends;
        uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
        uint32_t                    pipe_interleave_bytes;
@@ -147,6 +158,12 @@ struct radeon_info {
        /* Tile modes. */
        uint32_t                    si_tile_mode_array[32];
        uint32_t                    cik_macrotile_mode_array[16];
+
+       /* Hardware bugs. */
+       bool                        has_gfx9_scissor_bug;
+       bool                        has_tc_compat_zrange_bug;
+       bool                        has_msaa_sample_loc_bug;
+       bool                        has_ls_vgpr_init_bug;
 };
 
 bool ac_query_gpu_info(int fd, void *dev_p,
@@ -166,8 +183,12 @@ void ac_get_harvested_configs(struct radeon_info *info,
                              unsigned raster_config,
                              unsigned *cik_raster_config_1_p,
                              unsigned *raster_config_se);
+unsigned ac_get_compute_resource_limits(struct radeon_info *info,
+                                       unsigned waves_per_threadgroup,
+                                       unsigned max_waves_per_sh,
+                                       unsigned threadgroups_per_cu);
 
-static inline unsigned ac_get_max_simd_waves(enum radeon_family family)
+static inline unsigned ac_get_max_wave64_per_simd(enum radeon_family family)
 {
 
        switch (family) {
@@ -182,10 +203,26 @@ static inline unsigned ac_get_max_simd_waves(enum radeon_family family)
        }
 }
 
+static inline unsigned ac_get_num_physical_vgprs(enum chip_class chip_class,
+                                                unsigned wave_size)
+{
+       /* The number is per SIMD. */
+       if (chip_class >= GFX10)
+               return wave_size == 32 ? 1024 : 512;
+       else
+               return 256;
+}
+
 static inline uint32_t
-ac_get_num_physical_sgprs(enum chip_class chip_class)
+ac_get_num_physical_sgprs(const struct radeon_info *info)
 {
-       return chip_class >= GFX8 ? 800 : 512;
+       /* The number is per SIMD. There is enough SGPRs for the maximum number
+        * of Wave32, which is double the number for Wave64.
+        */
+       if (info->chip_class >= GFX10)
+               return 128 * ac_get_max_wave64_per_simd(info->family) * 2;
+
+       return info->chip_class >= GFX8 ? 800 : 512;
 }
 
 #ifdef __cplusplus