intel/aub_read: reuse defines from gen_context

[mesa.git] / src / amd / common / ac_gpu_info.h

diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 340c368bda3cfe1c69dcca44380e081fae3cdb9e..b1ef9c53734a3cc73f569f55a94b98b4c19dfd30 100644 (file)
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -47,6 +47,7 @@ struct radeon_info {
        uint32_t                    pci_func;
 
        /* Device info. */
+       const char                  *name;
        uint32_t                    pci_id;
        enum radeon_family          family;
        enum chip_class             chip_class;
@@ -86,7 +87,7 @@ struct radeon_info {
        uint32_t                    vce_fw_version;
        uint32_t                    vce_harvest_config;
 
-       /* Kernel info. */
+       /* Kernel & winsys capabilities. */
        uint32_t                    drm_major; /* version */
        uint32_t                    drm_minor;
        uint32_t                    drm_patchlevel;
@@ -100,11 +101,23 @@ struct radeon_info {
        bool                        htile_cmask_support_1d_tiling;
        bool                        si_TA_CS_BC_BASE_ADDR_allowed;
        bool                        has_bo_metadata;
+       bool                        has_gpu_reset_status_query;
+       bool                        has_gpu_reset_counter_query;
+       bool                        has_eqaa_surface_allocator;
+       bool                        has_format_bc1_through_bc7;
+       bool                        kernel_flushes_tc_l2_after_ib;
+       bool                        has_indirect_compute_dispatch;
+       bool                        has_unaligned_shader_loads;
+       bool                        has_sparse_vm_mappings;
+       bool                        has_2d_tiling;
+       bool                        has_read_registers_query;
 
        /* Shader cores. */
        uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
        uint32_t                    max_shader_clock;
        uint32_t                    num_good_compute_units;
+       uint32_t                    num_good_cu_per_sh;
+       uint32_t                    num_tcc_blocks;
        uint32_t                    max_se; /* shader engines */
        uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 
@@ -137,7 +150,8 @@ void ac_print_gpu_info(struct radeon_info *info);
 int ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family);
 void ac_get_raster_config(struct radeon_info *info,
                          uint32_t *raster_config_p,
-                         uint32_t *raster_config_1_p);
+                         uint32_t *raster_config_1_p,
+                         uint32_t *se_tile_repeat_p);
 void ac_get_harvested_configs(struct radeon_info *info,
                              unsigned raster_config,
                              unsigned *cik_raster_config_1_p,
@@ -158,6 +172,12 @@ static inline unsigned ac_get_max_simd_waves(enum radeon_family family)
        }
 }
 
+static inline uint32_t
+ac_get_num_physical_sgprs(enum chip_class chip_class)
+{
+       return chip_class >= VI ? 800 : 512;
+}
+
 #ifdef __cplusplus
 }
 #endif