ac: add has_msaa_sample_loc_bug to ac_gpu_info

[mesa.git] / src / amd / common / ac_gpu_info.h

diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 2c67cec3ed5692f4610c11ecd979f3f8f833c5a2..ba09f38edb872e7161926da8b37f1eacaef5c374 100644 (file)
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -35,8 +35,6 @@
 extern "C" {
 #endif
 
-/* Prior to C11 the following may trigger a typedef redeclaration warning */
-typedef struct amdgpu_device *amdgpu_device_handle;
 struct amdgpu_gpu_info;
 
 struct radeon_info {
@@ -53,10 +51,21 @@ struct radeon_info {
        uint32_t                    pci_id;
        enum radeon_family          family;
        enum chip_class             chip_class;
+       uint32_t                    family_id;
+       uint32_t                    chip_external_rev;
+       bool                        has_graphics; /* false if the chip is compute-only */
        uint32_t                    num_compute_rings;
        uint32_t                    num_sdma_rings;
        uint32_t                    clock_crystal_freq;
        uint32_t                    tcc_cache_line_size;
+       bool                        has_clear_state;
+       bool                        has_distributed_tess;
+       bool                        has_dcc_constant_encode;
+       bool                        has_rbplus; /* if RB+ registers exist */
+       bool                        rbplus_allowed; /* if RB+ is allowed */
+       bool                        has_load_ctx_reg_pkt;
+       bool                        has_out_of_order_rast;
+       bool                        cpdma_prefetch_writes_memory;
 
        /* There are 2 display DCC codepaths, because display expects unaligned DCC. */
        /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */
@@ -138,6 +147,7 @@ struct radeon_info {
        bool                        r600_gb_backend_map_valid;
        uint32_t                    r600_num_banks;
        uint32_t                    gb_addr_config;
+       uint32_t                    pa_sc_tile_steering_override; /* CLEAR_STATE also sets this */
        uint32_t                    num_render_backends;
        uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
        uint32_t                    pipe_interleave_bytes;
@@ -147,9 +157,14 @@ struct radeon_info {
        /* Tile modes. */
        uint32_t                    si_tile_mode_array[32];
        uint32_t                    cik_macrotile_mode_array[16];
+
+       /* Hardware bugs. */
+       bool                        has_gfx9_scissor_bug;
+       bool                        has_tc_compat_zrange_bug;
+       bool                        has_msaa_sample_loc_bug;
 };
 
-bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
+bool ac_query_gpu_info(int fd, void *dev_p,
                       struct radeon_info *info,
                       struct amdgpu_gpu_info *amdinfo);
 
@@ -166,6 +181,10 @@ void ac_get_harvested_configs(struct radeon_info *info,
                              unsigned raster_config,
                              unsigned *cik_raster_config_1_p,
                              unsigned *raster_config_se);
+unsigned ac_get_compute_resource_limits(struct radeon_info *info,
+                                       unsigned waves_per_threadgroup,
+                                       unsigned max_waves_per_sh,
+                                       unsigned threadgroups_per_cu);
 
 static inline unsigned ac_get_max_simd_waves(enum radeon_family family)
 {