const char *marketing_name;
bool is_pro_graphics;
uint32_t pci_id;
+ uint32_t pci_rev_id;
enum radeon_family family;
enum chip_class chip_class;
uint32_t family_id;
uint32_t chip_external_rev;
- bool has_graphics; /* false if the chip is compute-only */
- uint32_t num_compute_rings;
- uint32_t num_sdma_rings;
uint32_t clock_crystal_freq;
- uint32_t tcc_cache_line_size;
+
+ /* Features. */
+ bool has_graphics; /* false if the chip is compute-only */
+ uint32_t num_rings[NUM_RING_TYPES];
bool has_clear_state;
bool has_distributed_tess;
bool has_dcc_constant_encode;
bool has_rbplus; /* if RB+ registers exist */
+ bool rbplus_allowed; /* if RB+ is allowed */
bool has_load_ctx_reg_pkt;
bool has_out_of_order_rast;
bool cpdma_prefetch_writes_memory;
+ bool has_gfx9_scissor_bug;
+ bool has_tc_compat_zrange_bug;
+ bool has_msaa_sample_loc_bug;
+ bool has_ls_vgpr_init_bug;
+ /* Display features. */
/* There are 2 display DCC codepaths, because display expects unaligned DCC. */
/* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */
bool use_display_dcc_unaligned;
uint64_t gart_size;
uint64_t vram_size;
uint64_t vram_vis_size;
+ uint32_t vram_bit_width;
+ uint32_t vram_type;
unsigned gds_size;
unsigned gds_gfx_partition_size;
uint64_t max_alloc_size;
uint32_t min_alloc_size;
uint32_t address32_hi;
bool has_dedicated_vram;
+ bool has_l2_uncached;
bool r600_has_virtual_memory;
+ uint32_t num_sdp_interfaces;
+ uint32_t num_tcc_blocks;
+ uint32_t tcc_cache_line_size;
+ bool tcc_harvested;
+ unsigned pc_lines;
+ uint32_t lds_size_per_cu;
+ uint32_t lds_granularity;
+ uint32_t max_memory_clock;
+ uint32_t ce_ram_size;
+ uint32_t l1_cache_size;
+ uint32_t l2_cache_size;
/* CP info. */
bool gfx_ib_pad_with_type2;
uint32_t max_shader_clock;
uint32_t num_good_compute_units;
uint32_t num_good_cu_per_sh;
- uint32_t num_tcc_blocks;
uint32_t max_se; /* shader engines */
uint32_t max_sh_per_se; /* shader arrays per shader engine */
+ uint32_t max_wave64_per_simd;
+ uint32_t num_physical_sgprs_per_simd;
+ uint32_t num_physical_wave64_vgprs_per_simd;
+ uint32_t num_simd_per_compute_unit;
+ uint32_t min_sgpr_alloc;
+ uint32_t max_sgpr_alloc;
+ uint32_t sgpr_alloc_granularity;
+ uint32_t min_vgpr_alloc;
+ uint32_t max_vgpr_alloc;
+ uint32_t vgpr_alloc_granularity;
/* Render backends (color + depth blocks). */
uint32_t r300_num_gb_pipes;
uint32_t pipe_interleave_bytes;
uint32_t enabled_rb_mask; /* GCN harvest config */
uint64_t max_alignment; /* from addrlib */
+ uint32_t pbb_max_alloc_count;
/* Tile modes. */
uint32_t si_tile_mode_array[32];
unsigned max_waves_per_sh,
unsigned threadgroups_per_cu);
-static inline unsigned ac_get_max_simd_waves(enum radeon_family family)
-{
-
- switch (family) {
- /* These always have 8 waves: */
- case CHIP_POLARIS10:
- case CHIP_POLARIS11:
- case CHIP_POLARIS12:
- case CHIP_VEGAM:
- return 8;
- default:
- return 10;
- }
-}
-
-static inline uint32_t
-ac_get_num_physical_sgprs(enum chip_class chip_class)
-{
- return chip_class >= GFX8 ? 800 : 512;
-}
-
#ifdef __cplusplus
}
#endif